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    Pin Xcm001 A

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    adthvqs
    This document provides a pin mapping between an FPGA, two CNA connectors (CNA and CNB), a USB connector (CN5), an on-board clock, and an SRAM. It lists the pin numbers and labels for signals that connect different components on the board to the FPGA. These include power pins, ground pins, I/O pins for the two CNA connectors, clock signals, and address/data pins for interfacing with the SRAM.

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    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd

    Pin Xcm001 A

    Uploaded by

    adthvqs
    56 views4 pages
    This document provides a pin mapping between an FPGA, two CNA connectors (CNA and CNB), a USB connector (CN5), an on-board clock, and an SRAM. It lists the pin numbers and labels for signals that connect different components on the board to the FPGA. These include power pins, ground pins, I/O pins for the two CNA connectors, clock signals, and address/data pins for interfacing with the SRAM.

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    © Attribution Non-Commercial (BY-NC)

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    This document provides a pin mapping between an FPGA, two CNA connectors (CNA and CNB), a USB connector (CN5), an on-board clock, and an SRAM. It lists the pin numbers and labels for signals that connect different components on the board to the FPGA. These include power pins, ground pins, I/O pins for the two CNA connectors, clock signals, and address/data pins for interfacing with the SRAM.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
    Download as xls, pdf, or txt
    56 views4 pages

    Pin Xcm001 A

    Uploaded by

    adthvqs
    This document provides a pin mapping between an FPGA, two CNA connectors (CNA and CNB), a USB connector (CN5), an on-board clock, and an SRAM. It lists the pin numbers and labels for signals that connect different components on the board to the FPGA. These include power pins, ground pins, I/O pins for the two CNA connectors, clock signals, and address/data pins for interfacing with the SRAM.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
    Download as xls, pdf, or txt
    of 4

    BANK NET LABEL FPGA Pin CNA Pin FPGA Pin NET LABEL BANK BANK NET LABEL

    ET LABEL FPGA Pin CNB Pin FPGA Pin NET LABEL BANK

    3.3 V 3.3 V 3.3 V 3.3 V


    1 2 1 2
    (Input) (Input) (Input) (Input)
    Power Power Power Power
    3 4 3 4
    (Reserved) (Reserved) (Reserved) (Reserved)
    GND GND 5 6 GND GND GND GND 5 6 GND GND
    A IOA0 199 7 8 200 IOA1 A A 0 169 7 8 168 1 A
    A IOA2 203 9 10 204 IOA3 A A 2 167 9 10 166 3 A
    A IOA4 205 11 12 2 IOA5 A A 4 165 11 12 162 5 A
    A IOA6 3 13 14 4 IOA7 A A 6 161 13 14 156 7 B
    GND GND 15 16 GND GND GND GND 15 16 GND GND
    A IOA8 5 17 18 7 IOA9 A B 8 155 17 18 154 9 B
    A IOA10 9 19 20 10 IOA11 A B 10 152 19 20 150 11 B
    A IOA12 11 21 22 12 IOA13 A B 12 149 21 22 148 13 B
    A IOA14 13 23 24 15 IOA15 A B 14 147 23 24 146 15 B
    GND GND 25 26 GND GND GND GND 25 26 GND GND
    A IOA16 16 27 28 18 IOA17 A B 16 144 27 28 143 17 B
    A IOA18 19 29 30 20 IOA19 A B 18 141 29 30 140 19 B
    A IOA20 21 31 32 22 IOA21 A B 20 139 31 32 138 21 B
    A IOA22 24 33 34 26 IOA23 A B 22 137 33 34 135 23 B
    GND GND 35 36 GND GND GND GND 35 36 GND GND
    A IOA24 27 37 38 28 IOA25 A B 24 133 37 38 132 25 B
    A IOA26 29 39 40 31 IOA27 A B 26 131 39 40 130 27 B
    A IOA28 33 41 42 34 IOA29 A B 28 128 41 42 126 29 B
    A IOA30 35 43 44 36 IOA31 A B 30 125 43 44 124 31 B
    GND GND 45 46 GND GND GND GND 45 46 GND GND
    A IOA32 37 47 48 39 IOA33 A B 32 123 47 48 122 33 B
    A IOA34 40 49 50 42 IOA35 A B 34 120 49 50 119 35 B
    A IOA36 43 51 52 44 IOA37 A B 36 117 51 52 116 37 B
    A IOA38 45 53 54 46 IOA39 A B 38 115 53 54 114 39 B
    GND GND 55 56 GND GND GND GND 55 56 GND GND
    A IOA40 48 57 58 50 IOA41 A B 40 113 57 58 111 41 B
    A IOA42 51 59 60 52 IOA43 A B 42 109 59 60 108 43 B
    A IOA44 57 61 62 58 IOA45 A B 44 107 61 62 106 45 B
    A IOA46 61 63 64 62 IOA47 A A 46 102 63 64 101 47 A
    A IOA48 93 *1 65 66 90 IOA49 A A 48 96 65 66 95 49 A
    *1 Destination is selectable by jumper setting. (JP5) For more details, please
    see the circuit. schematic.
    CN5

    Pin NET LABEL FPGA Pin


    CN5-1 USBUMPA 93
    CN5-2 USBDMA 94
    CN5-3 USBDPA 97
    CN5-4 USBUPPA 100

    On board Clock

    Frequency NET LABEL FPGA Pin


    48MHz CLKA 80
    48MHz CLKB 79
    18.432MHz CLK2 180
    72KHz CLK3 181

    SRAM

    SRAM Pin NET LABEL FPGA Pin


    U7-1 RAM_A0 198
    U7-2 RAM_A1 197
    U7-3 RAM_A2 196
    U7-4 RAM_A3 194
    U7-5 RAM_A4 191
    U7-6 RAM_CE 182
    U7-7 RAM_D0 178
    U7-8 RAM_D1 176
    U7-9 V33_A V33_A
    U7-10 GND GND
    U7-11 RAM_D2 175
    U7-12 RAM_D3 172
    U7-13 RAM_WE 87
    U7-14 RAM_A5 86
    U7-15 RAM_A6 85
    U7-16 RAM_A7 78
    U7-17 RAM_A8 77
    U7-18 RAM_A9 67
    U7-19 N.C N.C
    U7-20 RAM_A10 65
    U7-21 RAM_A11 64
    U7-22 RAM_A12 63
    U7-23 RAM_A13 2
    U7-24 RAM_A14 190
    U7-25 RAM_D4 189
    U7-26 RAM_D5 187
    U7-27 V33_A V33_A
    U7-28 GND GND
    U7-29 RAM_D5 185
    U7-30 RAM_D6 74
    U7-31 RAM_D7 72
    U7-32 RAM_OE 71
    U7-33 RAM_A15 68
    U7-34 RAM_A17 76
    U7-35 RAM_A18 2
    U7-36 N.C N.C

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