Ordering number : ENN*6728

CMOS IC

LC651154N, 651154F, 651154L, LC651152N, 651152F, 651152L

Four-Bit CMOS Microcontrollers for
Small-Scale Control Applications

Preliminary

Overview — All ports:

· Are I/O ports
The LC651154N/F/L and the LC651152N/F/L are the
· I/O voltage handling capacity: 15 V (maximum)
small-scale control application versions of Sanyo’s
(Open-drain specification C, D, E, and F ports
LC6500 series of 4-bit single-chip CMOS
only)
microcontrollers, and feature the same basic architecture
· Output current: 20 mA (maximum) sink current
and instruction set. These microcontrollers include an 8-
(Are capable of directly driving an LED.)
input 8-bit A/D converter and are appropriate for use in a
— Support options to match application system
wide range of applications, from applications with a small
specifications
number of circuits and controls that were previously
A. Open-drain output, internal pull-up resistor
implemented in standard logic to applications with a larger
specification: All ports, in bit units
scale such as home appliances, automotive equipment,
B. Output level at reset specification: Ports C and D
communications equipment, office equipment, and audio
can be specified to go to the high or low level in
equipment such as decks and players. Also note that since
4-bit units.
these ICs provide the same basic functions (certain
• Interrupt function
functions and specifications do differ) as, and are pin
— Timer interrupts through an interrupt vector (Can be
compatible with the earlier LC651104N/F/L and
tested under program control)
LC651102N/F/L, they can replace those ICs in most cases.
— INT pin and serial I/O full/empty interrupts through
Features an interrupt vector (Can be tested under program
control)
• Fabricated in a CMOS process for low power (A
• Stack levels: 8 (Shared with the interrupt system.)
standby function that can be invoked under program
• Timers: 4-bit variable prescaler and 8-bit programmable
control is also provided.)
timers
• ROM/RAM
• Clock oscillator options that match a wide range of
LC651154N/F/L — ROM: 4K × 8 bits,
system specifications
RAM: 256 × 4 bits
— Oscillator circuit options:
LC651152N/F/L — ROM: 2K × 8 bits,
Two-pin RC oscillator (N and L versions)
RAM: 256 × 4 bits
Two-pin ceramic oscillator (N, F, and L versions)
• Instruction set: The 80-instruction set common to the
— Clock divider circuit options:
LC6500 family
No divider, built-in divide-by-3, built-in divide-by-4
• Wide operating supply voltage range: 2.2 to 6.0 V
(N and L versions)
(L versions)
• Continuous square wave output (with a period 64 times
• Instruction cycle time: 0.92 µs (F versions)
the cycle time)
• On-chip serial I/O function
• A/D converter (successive approximation)
• Flexible I/O ports
— 8-bit precision with 8 input channels
— Number of ports: 6 ports with a total of 22 pins
• Watchdog timer

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91799RM (OT) No. 6278-1/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

— RC circuit time constant

— Optional watchdog timer reset function from an
external pin

Function Table
Parameter LC651154N/1152N LC651154F/1152F LC651154L/1152L
4096 × 8 bits (1154N) 4096 × 8 bits (1154F) 4096 × 8 bits (1154L)
ROM
Memory 2048 × 8 bits (1152N) 2048 × 8 bits (1152F) 2048 × 8 bits (1152L)
RAM 256 × 4 bits (1154/1152N) 256 × 4 bits (1154/1152F) 256 × 4 bits (1154/1152L)
Instruction set 80 80 80
Instructions
Table reference Supported Supported Supported
Interrupts 1 external, 1 internal 1 external, 1 internal 1 external, 1 internal
4-bit variable prescaler 4-bit variable prescaler 4-bit variable prescaler
Timers
+ 8-bit timers + 8-bit timers + 8-bit timers
On-chip functions
Stack levels 8 8 8
Standby mode entered by the Standby mode entered by the Standby mode entered by the
Standby function
HALT instruction supported HALT instruction supported HALT instruction supported
Number of ports 22 I/O port pins 22 I/O port pins 22 I/O port pins
Serial port Input and output in 4 or 8 bit units Input and output in 4 or 8 bit units Input and output in 4 or 8 bit units
I/O voltage handling capability 15 V max. 15 V max. 15 V max.
I/O ports Output current 10 mA typ. 20 mA max. 10 mA typ. 20 mA max. 10 mA typ. 20 mA max.
I/O circuit types Open drain (n-channel) and pull-up resistor output options can be specified in 1-bit units
Output level at reset A high or low level output can be selected in port units (ports C and D only)
Square wave output Supported Supported Supported
Minimum cycle time 2.77 µs (VDD ≥ 3 V) 0.92 µs (VDD ≥ 2.5 V) 3.84 µs (VDD ≥ 2.2 V)
Characteristics Supply voltage 3 to 6 V 2.5 to 6 V 2.2 to 6 V
Current drain 1.5 mA typ. 2 mA typ. 1.5 mA typ.
RC (800/400 kHz typ.) RC (400 kHz typ.)
Oscillator element Ceramic 4 MHz
Oscillator Ceramic (400 k, 800 k, 1 MHz, 4 MHz) Ceramic (400 k, 800 k, 1 MHz, 4 MHz)
Divider circuit option 1/1, 1/3, 1/4 1/1 1/1, 1/3, 1/4
Other items Package DIP30S-D, MFP30S, SSOP30 DIP30S-D, MFP30S, SSOP30 DIP30S-D, MFP30S, SSOP30

Note: Recommendations for oscillator elements and oscillator circuit constants will be announced as the recommended circuits for these ICs are determined.
Verify the progress of these developments periodically.

No. 6278-2/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Differences between the LC651154N/1152N and the LC651104N/1102N.

The table below lists the points that require care when converting an existing product that uses the LC651104N/1102N to
use the LC651154N/1152N.

Parameter LC651154N/1152N LC651104N/1102N

Pdmax (1) : DIP 310 mW 250 mW
Allowable power dissipation Pdmax (2) : MFP 220 mW 150 mW
Pdmax (3) : SSOP 160 mW (No corresponding package)
Oscillator frequency precision: within ±2%
fCFOSC
Changes in the recommended oscillator Oscillator frequency precision: within ±4%
[OSC1, OSC2]
constants (See table 1.)
Oscillator characteristics
800 kHz typ. (VDD = 3 to 6 V) 900 kHz typ. (VDD = 4 to 6 V)
Ceramic oscillator
Constants changed: Rext = 5.6 kΩ ±1 % Constants changed: Rext = 4.7 kΩ ±1 %
Oscillator frequency
Frequency variability (sample to sample): Frequency variability (sample to sample):
2-pin RC oscillator fMOSC
587 to 1298 kHz 634 to 1278 kHz
Oscillator frequency [OSC1, OSC2]
400 kHz typ. (VDD = 3 to 6 V) 400 kHz typ. (VDD = 3 to 6 V)
Frequency variability (sample to sample): Frequency variability (sample to sample):
290 to 616 kHz 276 to 742 kHz
Pull-up resistors Ru [RES] 200 to 800 kΩ (500 kΩ typ.) 300 to 700 kΩ (500 kΩ typ.)
Serial clock input clock cycle time tCKCY (1) [ SCK] min. 2.0 µs min. 3.0 µs
A/D converter characteristics Operating voltage VDD = 3 to 6 V VDD = 4 to 6 V
AV+ = VDD Reference input current
200 to 800 µA (500 µA typ.) 75 to 300 µA (150 µA typ.)
AV– = VSS IRIF [AV+, AV–]
Watchdog timer
Cw = 0.047 ±5% µF
VDD = 3 to 6 V VDD = 4 to 6 V
Rw = 680 ±1% kΩ
RI = 100 ±1% Ω
DIP30S-D, MFP30S
Package DIP30S-D, MFP30S
An SSOP30 version was added.

Differences between the LC651154F/1152F and the LC651104F/1102F.

The table below lists the points that require care when converting an existing product that uses the LC651104F/1102F to
use the LC651154F/1152F.

Parameter LC651154F/1152F LC651104F/1102F

Pdmax (1) : DIP 310 mW 250 mW
Allowable power dissipation Pdmax (2) : MFP 220 mW 150 mW
Pdmax (3) : SSOP 160 mW (No corresponding package)
Operating supply voltage VDD 2.5 to 6 V 4 to 6 V
Specifications for VDD = 4 to 6 V
Low-level input voltage VIL(n) The specifications for VDD = 2.5 to 6 V Specifications for VDD = 4 to 6 V
were added.
Oscillator characteristics
fCFOSC
Ceramic oscillator Oscillator frequency precision: within ±2 % Oscillator frequency precision: within ±4 %
[OSC1, OSC2]
Oscillator frequency
Pull-up resistors Ru [RES] 200 to 800 kΩ (500 kΩ typ.) 300 to 700 kΩ (500 kΩ typ.)
AD speed 1/1 : VDD = 3.5 to 6 V AD speed 1/1 : VDD = 4.5 to 6 V
A/D converter characteristics Operating voltage
AD speed 1/2 : VDD = 3 to 6 V AD speed 1/2 : VDD = 4 to 6 V
AV+ = VDD
Reference input current
AV– = VSS 200 to 800 µA (500 µA typ.) 75 to 300 µA (150 µA typ.)
IRIF [AV+, AV–]
DIP30S-D, MFP30S
Package DIP30S-D, MFP30S
An SSOP30 version was added.

No. 6278-3/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Differences between the LC651154L/1152L and the LC651104L/1102L.

The table below lists the points that require care when converting an existing product that uses the LC651104L/1102L to
use the LC651154L/1152L.

Parameter LC651154L/1152L LC651104L/1102L

Pdmax (1) : DIP 310 mW 250 mW
Allowable power dissipation Pdmax (2) : MFP 220 mW 150 mW
Pdmax (3) : SSOP 160 mW (No corresponding package)
Operating supply voltage VDD 2.2 to 6 V 2.5 to 6 V
Oscillator frequency precision: within ±2%
Oscillator characteristics fCFOSC
Changes in the recommended oscillator Oscillator frequency precision: within ±4%
Ceramic oscillator [OSC1, OSC2]
constants (See table 1.)
Oscillator frequency
400 kHz typ. (VDD = 2.2 to 6 V) 400 kHz typ. (VDD = 2.5 to 6 V)
2-pin RC oscillator fMOSC
Frequency variability (sample to sample): Frequency variability (sample to sample):
Oscillator frequency [OSC1, OSC2]
290 to 841 kHz 276 to 742 kHz
Pull-up resistors Ru [RES] 200 to 800 kΩ (500 kΩ typ.) 300 to 700 kΩ (500 kΩ typ.)
Serial clock input clock cycle time tCKCY (1) [ SCK] min. 2.0 µs min. 6.0 µs
A/D converter characteristics Operating voltage VDD = 3 to 6 V VDD = 4 to 6 V
AV+ = VDD Reference input current
200 to 800 µA (500 µA typ.) 75 to 300 µA (150 µA typ.)
AV– = VSS IRIF [AV+, AV–]
Watchdog timer VDD = 2.2 to 6.0 V VDD = 2.5 to 6.0 V
DIP30S-D, MFP30S
Package DIP30S-D, MFP30S
An SSOP30 version was added.

Caution: Perform a full system evaluation and inspection after replacing the microcontroller.

No. 6278-4/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Pin Assignment

The pin assignment is the same for the DIP, MFP, and SSOP packages.

No. 6278-5/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Pin Functions
OSC1, OSC2: Connections for the oscillator capacitor and resistor or ceramic element TEST: IC testing.
RES: Reset INT: Interrupt request input
PA0 to PA3: Common I/O ports A0 to A3 SI: Serial input
PC0 to PC3: Common I/O ports C0 to C3 SO: Serial output
PD0 to PD3: Common I/O ports D0 to D3 SCK: Serial clock input output
PE0 to PE3: Common I/O ports E0 to E3 AD0 to AD7: A/D converter analog inputs
PF0 to PF3: Common I/O ports F0 to F3 AV+, AV–: A/D converter reference voltage inputs
PG0 to PG3: Common I/O ports G0 to G3 WDR: Watchdog timer reset input
Note: Pins SI, SO, SCK, and INT are shared function pins also used as PF0:3.

System Block Diagram

Shared with port F

RAM: Data memory ROM: Program memory

F: Flag PC: Program counter
WR: Working register INT: Interrupt control
AC: Accumulator IR: Instruction register
ALU: Arithmetic and logic unit I.DEC: Instruction decoder
DP: Data pointer CF, CSF: Carry flag and carry save flag
E: E register ZF, ZSF: Zero flag and zero save flag
CTL: Control register EXTF: External interrupt request flag
OSC: Oscillator circuit TMF: Internal interrupt request flag
TM: Timer
STS: Status register

No. 6278-6/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Development Support
The following are provided for development with the LC651154 and LC651152.

• User’s manual
See the “LC651104/1102 User’s Manual.”
• Development tools manual
See the “Four-Bit Microcontroller EVA86000 Development Tools Manual.”
• Software manual
“LC65/66 Series Software Manual”
• Development tools
— Program development (EVA86000 System)
— On-chip EPROM microcontroller <LC65E1104> for program evaluation

Pin Functions
Number Handling when
Symbol I/O Function Option At reset
of pins unused
VDD —
1 Power supply — — —
VSS —

(1) Two-pin RC oscillator or

OSC1 1 Input external clock
• Connection for the RC circuit or ceramic oscillator
(2) Two-pin ceramic oscillator
element used for the system clock oscillator
(3) Divider option — —
• Leave OSC2 open when an external clock input is
1. No divider
Output used.
OSC2 1 2. Divide-by-3
3. Divide-by-4

• I/O port A0 to A3
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Testing in 1-bit units (BP and BNP instructions)
Set and reset in 1-bit units (SPB and RPB
High-level
instructions) Select the
PA0 to (1) Open-drain output output (The
• PA3 is used for standby mode control open-drain
PA3/ (2) Pull-up resistor output n-
4 I/O • Application must assure that chattering does not output option
AD0 to Options (1) and (2) can be channel
occur on the PA3 input during HALT instruction and connect
AD3 specified in bit units transistors in
execution. to VSS.
the off state.)
• All four pins have shared functions
PA0/AD0 - A/D converter input AD0
PA1/AD1 - A/D converter input AD1
PA2/AD2 - A/D converter input AD2
PA3/AD3 - A/D converter input AD3

(1) Open-drain output • High-level

• I/O port C0 to C3
(2) Pull-up resistor output
The port functions are identical to those of PA0 to
(3) High-level output during reset
PA3. (See note.) • Low-level The same as
PC0 to (4) Low-level output during reset
4 I/O • The output during a reset can be selected to be output for PA0 to
PC3 • Options (1) and (2) can be
either high or low as an option. (Depending PA3
specified in bit units
Note: This port has no standby mode control on option
• Options (3) and (4) are
function. selected.)
specified 4 bits at a time

• I/O port D0 to D3 The same as

PD0 to The same as
4 I/O The port functions and options are identical to The same as PC0 to PC3 for PA0 to
PD3 PC0 to PC3
those of PC0 to PC3. PA3

Continued on next page.

No. 6278-7/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Number Handling when

Symbol I/O Function Option At reset
of pins unused
• I/O port E0 to E1
Input in 4-bit units (IP instruction) (1) Open-drain output
Output in 4-bit units (OP instruction) (2) Pull-up resistor
High-level
Set and reset in 1-bit units (SPB and RPB • Options (1) and (2) can be output (The
PE0-PE1/ specified in bit units Identical to
instructions) output n-
2 I/O those for PA0
WDR Testing in 1-bit units (BP and BNP instructions) (3) Normal port PE1 channel
to PA3
transistors in
• PE0 also has a continuous pulse (64·Tcyc) output (4) Watchdog reset WDR
the off state.)
function. • Either options (3) and (4)
• PE1 becomes the watchdog reset pin WDR when may be specified.
selected for such as an option.

• I/O port F0 to F3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
• PF0 to PF3 have shared functions as the serial Identical to
interface pins and the INT input. those for PA0
PF0/SI The function can be selected under program to PA3

PF1/SO control. The serial port Identical to

4 I/O SI ... Serial input pin Identical to those for PA0 to PA3 functions are those for PA0
PF2/SCK disabled. to PA3
PF3/INT SO ... Serial output pin
The interrupt
SCK ... Input and output of the serial clock signal source is set
INT ... Interrupt request input to INT.
The serial I/O function can be switched between 4-
bit and 8-bit transfers under program control.
Note: There is no continuous pulse output function.

• I/O port G0 to G3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
Note: There is no continuous pulse output function.
PG0-PG3/ Identical to Identical to
4 I/O • All four pins have shared functions. Identical to those for PA0 to PA3 those for PA0 those for PA0
AD4-AD7 to PA3 to PA3
PG0/AD4 - A/D converter input AD4
PG1/AD5 - A/D converter input AD5
PG2/AD6 - A/D converter input AD6
PG3/AD7 - A/D converter input AD7
AV+ 1 — Connect to
A/D converter reference voltage input — —
AV– 1 — VSS.

• System reset input

• Applications must provide an external capacitor for
RES 1 Input the power-on reset. — — —
• Apply a low level to this pin for 4 clock cycles to
effect and reset start.
• IC test pin This pin must
TEST 1 Input This pin must be connected to VSS during normal — — be connected
operation. to VSS.

No. 6278-8/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Oscillator Circuit Options

Option Circuit Conditions and other notes

External clock The OSC2 pin must be left open.

Two-pin RC oscillator

Ceramic oscillator Ceramic

oscillator element

Divider Circuit Options

Option Circuit Conditions and other notes

• This option can be used with any of the three oscillator

options.
Oscillator circuit

generator

• The oscillator frequency or external clock frequency must

Timing

No divider not exceed 1444 kHz. (LC651154N, LC651152N)

• The oscillator frequency or external clock frequency must
not exceed 4330 kHz. (LC651154F, LC651152F)
• The oscillator frequency or external clock frequency must
not exceed 1040 kHz. (LC651154L, LC651152L)
Oscillator circuit

• This option can only be used with the external clock and the
generator
Timing

Built-in divide-by-three circuit ceramic oscillator options.

Divide-by-3
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.
Oscillator circuit

• This option can only be used with the external clock and the
generator
Timing

Built-in divide-by-four circuit Divide-by-4 ceramic oscillator options.

• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.

Caution: The following tables summarize the oscillator and divider circuit options. Use care when selecting these options.

No. 6278-9/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Oscillator Options

LC651154N, LC651152N
Divider option
Circuit type Frequency VDD range Notes
(cycle time)
Cannot be used with the divide-by-three
400 kHz 1/1 (10 µs) 3 to 6 V
and divide-by-four options.
1/1 (5 µs) 3 to 6 V
800 kHz 1/3 (15 µs) 3 to 6 V
1/4 (20 µs) 3 to 6 V
Ceramic oscillator
1/1 (4 µs) 3 to 6 V
1 MHz 1/3 (12 µs) 3 to 6 V
1/4 (16 µs) 3 to 6 V
1/3 (3 µs) 3 to 6 V Cannot be used with the no divider circuit
4 MHz
1/4 (4 µs) 3 to 6 V option.
200 k to 1444 kHz 1/1 (20 to 2.77 µs) 3 to 6 V
External clock used with the 2-pin RC oscillator circuit 600 k to 4330 kHz 1/3 (20 to 2.77 µs) 3 to 6 V
800 k to 4330 kHz 1/4 (20 to 3.70 µs) 3 to 6 V
Use the no divider circuit option and the 3 to 6 V
recommended circuit constants. If using other circuit
Two-pin RC constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
External clock used with the ceramic oscillator option External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.

LC651154F, LC651152F
Divider option
Circuit type Frequency VDD range Notes
(cycle time)
Ceramic oscillator 4 MHz 1/1 (1 µs) 2.5 to 6 V
External clock used with the 2-pin RC oscillator circuit 200 k to 4330 kHz 1/1 (20 to 0.92 µs) 2.5 to 6 V
External clock used with the ceramic oscillator option External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.

No. 6278-10/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

LC651154L, LC651152L
Divider option
Circuit type Frequency VDD range Notes
(cycle time)
Cannot be used with the divide-by-three
400 kHz 1/1 (10 µs) 2.2 to 6 V and divide-by-four options.
1/1 (5 µs) 2.2 to 6 V
800 kHz 1/3 (15 µs) 2.2 to 6 V
1/4 (20 µs) 2.2 to 6 V
Ceramic oscillator 1/1 (4 µs) 2.2 to 6 V
1 MHz 1/3 (12 µs) 2.2 to 6 V
1/4 (16 µs) 2.2 to 6 V

Cannot be used with either the no divider

4 MHz 1/4 (4 µs) 2.2 to 6 V circuit option or the divide-by-three circuit
option.

200 k to 1040 kHz 1/1 (20 to 3.84 µs) 2.2 to 6 V

External clock used with the 2-pin RC oscillator circuit 600 k to 3120 kHz 1/3 (20 to 3.84 µs) 2.2 to 6 V
800 k to 4160 kHz 1/4 (20 to 3.84 µs) 2.2 to 6 V
Use the no divider circuit option and the 2.2 to 6 V
recommended circuit constants. If using other circuit
Two-pin RC constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
External clock used with the ceramic oscillator option External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.

Port C and D Output Level During Reset Option

The output level during a reset can be selected from the two options below in 4-bit units for the C and D ports.

Option Conditions and other notes

High-level output during reset Ports C and D in 4-bit units
Low-level output during reset Ports C and D in 4-bit units

Port Output Type Option

The following two options may be selected for the I/O ports individually (bit units).

Option Circuit Applicable ports

1. Open-drain output

Ports A, C, D, E, F, and G

2. Built-in pull-up resistor

Watchdog Reset Option

This option allows the PE1/WDR pin to be selected either to be used as the normal port PE1 or to be used as the
watchdog reset pin WDR.

No. 6278-11/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

LC651154N, 651152N

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter Symbol Conditions Applicable pins and notes Ratings Unit

Maximum supply voltage VDD max VDD –0.3 to +7.0
Allowed up to the
Output voltage VO OSC2
generated voltage.
VI (1) OSC1 *1 –0.3 to VDD + 0.3
Input voltage V
VI (2) TEST, RES, AV+, AV– –0.3 to VDD + 0.3
VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 Open-drain specification ports –0.3 to +15
I/O voltage VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 Pull-up resistor specification ports –0.3 to VDD + 0.3
VIO (3) PC0 to 3, PG0 to 3 –0.3 to VDD + 0.3
Peak output current IOP I/O ports –2 to +20
IOA Per single pin, averaged over 100 ms I/O ports –2 to +20
PC0 to 3
The total current for PC0 to PC3,
∑IOA (1) PD0 to 3 –15 to +100
PD0 to PD3, and PE0 to PE1 *2 mA
Average output current PE0 to 1
PF0 to 3
The total current for PF0 to PF3,
∑IOA (2) PG0 to 3 –15 to +100
PG0 to PG3, and PA0 to PA3 (See note 2.) *2
PA0 to 3
Pd max (1) Ta = –40 to +85°C (DIP package) 310
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package) 220 mW
Pd max (3) Ta = –40 to +85°C (SSOP package) 160
Operating temperature Topr –40 to +85
°C
Storage temperature Tstg –55 to +125

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Operating supply voltage VDD VDD 3.0 6.0
Standby supply voltage VST RAM and register values retained*3 VDD 1.8 6.0
Ports C, D, E, and F with
VIH (1) Output n-channel transistors off 0.7 VDD 13.5
open-drain specifications
Ports C, D, E, and F with
VIH (2) Output n-channel transistors off 0.7 VDD VDD
pull-up resistor specifications
VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD V
The INT, SCK, and SI
High-level input voltage VIH (4) Output n-channel transistors off pins with open-drain 0.8 VDD 13.5
specifications
The INT, SCK, and SI
VIH (5) Output n-channel transistors off pins with pull-up resistor 0.8 VDD VDD
specifications
VIH (6) VDD = 1.8 to 6.0 V RES 0.8 VDD VDD
VIH (7) External clock specifications OSC1 0.8 VDD VDD

Continued on next page.

No. 6278-12/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
VIL (1) Output n-channel transistors off VDD = 4 to 6 V Port VSS 0.3 VDD
VIL (2) Output n-channel transistors off VDD = 3 to 6 V Port VSS 0.25 VDD
VIL (3) Output n-channel transistors off VDD = 4 to 6 V INT, SCK, SI VSS 0.25 VDD
VIL (4) Output n-channel transistors off VDD = 3 to 6 V INT, SCK, SI VSS 0.2 VDD
VIL (5) External clock specifications VDD = 4 to 6 V OSC1 VSS 0.25 VDD V
Low-level input voltage
VIL (6) External clock specifications VDD = 3 to 6 V OSC1 VSS 0.2 VDD
VIL (7) VDD = 4 to 6 V TEST VSS 0.3 VDD
VIL (8) VDD = 3 to 6 V TEST VSS 0.25 VDD
VIL (9) VDD = 4 to 6 V RES VSS 0.25 VDD
VIL (10) VDD = 3 to 6 V RES VSS 0.2 VDD
The clock may have a
frequency up to 4.33 MHz
Operating frequency when either the divide-by- 200 1444
fop (Tcyc) VDD = 3 to 6 V kHz (µs)
(cycle time) three or divide-by-four (20) (2.77)
internal divider circuit option
is used.
External clock conditions Figure 1.
Frequency text Either the divide-by- VDD = 3 to 6 V OSC1 200 4330 kHz
three or divide-by-four
internal divider circuit
Pulse width textH, textL must be used if the VDD = 3 to 6 V OSC1 69
clock frequency ns
Rise and fall times textR, textF exceeds 1.444 MHz. VDD = 3 to 6 V OSC1 50

Recommended oscillator
circuit constants Cext 270 ±5% pF
Figure 2 VDD = 3 to 6 V OSC1, OSC2
Rext 12 ±1% kΩ
Two-pin RC oscillator
Cext 270 ±5% pF
Figure 2 VDD = 3 to 6 V OSC1, OSC2
Rext 5.6 ±1% kΩ
Ceramic oscillator *4 Figure 3 See table 1.

No. 6278-13/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
• Output n-channel transistors off
Ports C, D, E and F with
(Including the n-channel transistor
IIH (1) the open-drain 5.0
off leakage current.)
specifications
• VIN = 13.5 V
• Output n-channel transistors off
High-level input current
(Including the n-channel transistor Ports A and G with the µA
IIH (2) 1.0
off leakage current.) open-drain specifications
• VIN = VDD
When an external clock is used,
IIH (3) OSC1 1.0
VIN = VDD
• Output n-channel transistors off Ports with the open-drain
IIL (1) –1.0
• VIN = VSS specifications
• Output n-channel transistors off Ports with the pull-up
IIL (2) –1.3 –0.35 mA
Low-level input current • VIN = VSS resistor specifications
IIL (3) VIN = VSS RES –45 –10
When an external clock is used, OSC1 –1.0 µA
IIL (4)
VIN = VSS
• IOH = –50 µA Ports with the pull-up
VOH (1) VDD – 1.2
• VDD = 4.0 to 6.0 V resistor specifications
High-level output voltage
Ports with the pull-up
VOH (2) IOH = –10 µA VDD – 0.5
resistor specifications
• IOL = 10 mA
VOL (1) Port 1.5
• VDD = 4.0 to 6.0 V
Low-level output voltage
When IOL = 1 mA and the IOL for V
VOL (2) Port 0.5
each port is 1 mA or less.
Schmitt characteristics

Hysteresis voltage VHIS 0.1 VDD

RES, INT, SCK, SI, and
High-level threshold
VtH OSC1 with Schmitt 0.4 VDD 0.8 VDD
voltage
specifications*5
Low-level threshold
VtL 0.2 VDD 0.6 VDD
voltage
Current drain *6 • Operating, with the output
n-channel transistors off
IDDOP (1) VDD 1.5 4
Two-pin RC oscillator • With the ports at VDD
• Figure 2, fosc = 800 kHz (typical)
Ceramic oscillator IDDOP (2) • Figure 3, 4 MHz, divide-by-three circuit used VDD 1.5 5
IDDOP (3) • Figure 3, 4 MHz, divide-by-four circuit used VDD 1.5 4
IDDOP (4) • Figure 3, 400 kHz VDD 1.0 2.5 mA
IDDOP (5) • Figure 3, 800 kHz VDD 1.5 4
• 200 kHz to 1444 kHz, no divider
circuit
• 600 kHz to 4330 kHz, divide-by-
External clock IDDOP (6) three circuit used VDD 1.5 5
• 800 kHz to 4330 kHz, divide-by-
four circuit used
Output n-channel transistors off, VDD 0.05 10
Standby mode IDDst VDD = 6 V µA
Ports at VDD, VDD = 3 V VDD 0.025 5

Continued on next page.

No. 6278-14/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Oscillator characteristics • Figure 3, fo = 400 kHz OSC1, OSC2 392 400 408
• Figure 3, fo = 800 kHz OSC1, OSC2 784 800 816
Ceramic oscillator • Figure 3, fo = 1 MHz OSC1, OSC2 980 1000 1020
fCFOSC*7 kHz
Oscillator frequency • Figure 3, fo = 4 MHz, with the OSC1, OSC2 3920 4000 4080
divide-by-three or divide-by-four
circuit used.
Oscillator stabilization time • Figure 4, fo = 400 kHz 10
(note 8) • Figure 4, fo = 800 kHz, 1 MHz, or 10
tCFS ms
4 MHz, with the divide-by-three or
divide-by-four circuit used.
Two-pin RC oscillator • Figure 2, Cext = 270 pF ±5%
OSC1, OSC2 587 800 1298
Oscillator frequency • Figure 2, Rext = 5.6 kΩ ±1%
fMOSC kHz
• Figure 2, Cext = 270 pF ±5%
OSC1, OSC2 290 400 818
• Figure 2, Rext = 12 kΩ ±1%
Pull-up resistor • Output n-channel transistors off Pull-up resistor
RPP 8 14 30
I/O ports • VIN = VSS, VDD = 5 V specification ports kΩ
RES Ru VIN = VSS, VDD = 5 V RES 200 500 800
External reset characteristics
tRST See figure 5.
Reset time
• f = 1 MHz
Pin capacitances Cp • With all pins other than the pin 10 pF
being tested at VIN = VSS.
Serial clock
tCKCY (1) Figure 6 SCK 2.0
Input clock cycle time
Output clock cycle time tCKCY (2) Figure 6 SCK 64 × TCYC*9
Input clock low-level pulse
tCKL (1) Figure 6 SCK 1.0
width
Output clock low-level pulse
tCKL (2) Figure 6 SCK 32 × TCYC
width
Input clock high-level pulse
tCKH (1) Figure 6 SCK 1.0
width
Output clock high-level
tCKH (2) Figure 6 SCK 32 × TCYC
pulse width
µs
Serial input
• Stipulated with respect to the
rising edge of SCK. SI 0.4
Data setup time tICK
• Figure 6

Data hold time tCKI SI 0.4

Serial output • Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
Output delay time tCKO and an external capacitor of 50 pF SO 0.6
on only the n-channel open-drain
pins.
• Figure 6

Continued on next page.

No. 6278-15/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
Pulse output function
• Figure 7
Period tPCY • TCYC = 4 × system clock PE0 64 × TCYC
period
• With an external resistor of
High-level pulse width tPH 1 kΩ and an external PE0 32 × TCYC
µs
capacitor of 50 pF on only ±10%
the n-channel open-drain
32 × TCYC
Low-level pulse width tPL pins. PE0
±10%
Resolution 8 bit
AV+ = VDD
Absolute precision ±1 ±2 LSB
AV– = VSS
When the A/D converter 72 312
speed is normal (1:1), (TCYC = (TCYC =
namely 26 × TCYC 2.77 µs) 12 µs)
Conversion time TCAD µs
A/D converter characteristics

When the A/D converter 141 612

speed is one half (1:2), (TCYC = (TCYC =
namely 51 × TCYC 2.77 µs) 12 µs)
AV+ AV+ AV– VDD
Input reference voltage V
AV– VDD = 3 to 6 V AV– VSS AV+
Input reference current
IRIF AV+ = VDD, AV– = VSS AV+, AV– 200 500 800 µA
range
Analog input voltage
VAIN AD0 to AD7 AV– AV+ V
range
Including the output off AD0 to AD7 1
leakage current. (The I/O
VAIN = VDD shared
Analog port input current IAIN function ports µA
have open-
VAIN = VSS –1
drain
specifications.)
When PE1 has the
Cw WDR 0.1 ±5% µF
open-drain specifications.
Recommended When PE1 has the
Rw WDR 680 ±1% kΩ
constants*10 open-drain specifications.
VDD = 3 to 6 V
When PE1 has the
RI WDR 100 ±1% Ω
open-drain specifications.
Watchdog timer

Clear time (discharge) tWCT Figure 8 WDR 100 µs

Clear period (charge) tWCCY Figure 8 WDR 36 ms
When PE1 has the
Cw WDR 0.047 ±5% µF
open-drain specifications.
Recommended When PE1 has the
Rw WDR 680 ±1% kΩ
constants*10 open-drain specifications.
VDD = 3 to 6 V
When PE1 has the
RI WDR 100 ±1% Ω
open-drain specifications.
Clear time (discharge) tWCT Figure 8 WDR 40 µs
Clear period (charge) tWCCY Figure 8 WDR 18 ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range.
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.

No. 6278-16/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

External clock open

Figure 1 External Clock Input Waveform

Ceramic oscillator
element

Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit

No. 6278-17/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Lower limit for the operating supply voltage

Stable oscillation
Oscillation
stabilization
time tCFS

Figure 4 Oscillation Stabilization Time

Table 1 Recommended Ceramic Oscillator Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MG C2 33 pF ±10%
CST4.00MGW (Internal capacitor) R 0Ω
4 MHz (Kyocera Corporation) C1 33 pF ±10%
KBR4.0MSA C2 33 pF ±10%
KBR4.0MKS (Internal capacitor) R 0Ω
1 MHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10%
CSB1000J C2 100 pF ±10%
R 3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10% Figure 5 Reset Circuit
CSB800J C2 100 pF ±10%
R 3.3 kΩ
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
400 kHz (Murata Mfg. Co., Ltd.) C1 220 pF ±10% will be between 10 and 100 ms.
CSB400P C2 220 pF ±10% If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
R 3.3 kΩ

No. 6278-18/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Input data
Load circuit

Output data

Figure 6 Serial I/O Timing

The load conditions are the same

as those in figure 5.

Figure 7 Port PE0 Pulse Output Timing

tWCCY: The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT: The discharge time due to software processing.

Figure 8 Watchdog Timer Waveform

No. 6278-19/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

RC Oscillator Characteristics for the LC651154N and LC651152N

Figure 9 shows the RC oscillator characteristics for the LC651154N and LC651152N.
However, the sample-to-sample variation in the LC651154N and LC651152N RC oscillator frequency described below
does occur.
1) When:
VDD = 3.0 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
fMOSC will be:
290 kHz ≤ fMOSC ≤ 818 kHz
2) When:
VDD = 3.0 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 5.6 kΩ
fMOSC will be:
587 kHz ≤ fMOSC ≤ 1298 kHz
Therefore, only the above circuit constants are recommended.

If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)

Notes • The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25°C.
• Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range VDD = 3.0 to 6.0 V and for
the temperature range Ta = –40 to +85°C.

These characteristics curves are for

reference purposes only and are not
guaranteed.

Figure 9 RC Oscillator Frequency Data (Representative Values)

No. 6278-20/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

LC651154F, 651152F

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter Symbol Conditions Applicable pins and notes Ratings Unit
Maximum supply voltage VDD max VDD –0.3 to +7.0
Allowed up to the
Output voltage VO OSC2
generated voltage.
VI (1) OSC1 *1 –0.3 to VDD + 0.3
Input voltage V
VI (2) TEST, RES, AV+, AV– –0.3 to VDD + 0.3
VIO (1) PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports –0.3 to +15
I/O voltage VIO (2) PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports –0.3 to VDD + 0.3
VIO (3) PA0 to PA3, PG0 to PG3 –0.3 to VDD + 0.3
Peak output current IOP I/O ports –2 to +20
IOA Per single pin, averaged over 100 ms I/O ports –2 to +20
PC0 to PC3
The total current for PC0 to PC3,
∑IOA (1) PD0 to PD3 –15 to +100
PD0 to PD3, and PE0 and PE1 *2 mA
Average output current PE0 and PE1
PF0 to PF3
The total current for PF0 to PF3, PG0 to PG3,
∑IOA (2) PG0 to PG3 –15 to +100
and PA0 to PA3 (See note 2.) *2
PA0 to PA3
Pd max (1) Ta = –40 to +85°C (DIP package) 310
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package) 220 mW
Pd max (3) Ta = –40 to +85°C (SSOP package) 160
Operating temperature Topr –40 to +85
°C
Storage temperature Tstg –55 to +125

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Operating supply voltage VDD VDD 2.5 6.0
Standby supply voltage VST RAM and register values retained*3 VDD 1.8 6.0
Ports C, D, E, and F with
VIH (1) Output n-channel transistors off 0.7 VDD 13.5
open-drain specifications
Ports C, D, E, and F with
VIH (2) Output n-channel transistors off 0.7 VDD VDD
pull-up resistor specifications
VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD V
The INT, SCK, and SI
High-level input voltage VIH (4) Output n-channel transistors off pins with open-drain 0.8 VDD 13.5
specifications
The INT, SCK, and SI
VIH (5) Output n-channel transistors off pins with pull-up resistor 0.8 VDD VDD
specifications
VIH (6) VDD = 1.8 to 6.0 V RES 0.8 VDD VDD
VIH (7) External clock specifications OSC1 0.8 VDD VDD

Continued on next page.

No. 6278-21/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
VIL (1) Output n-channel transistors off VDD = 4 to 6 V Port VSS 0.3 VDD
VIL (2) Output n-channel transistors off VDD = 2.5 to 6 V Port VSS 0.2 VDD
VIL (3) Output n-channel transistors off VDD = 4 to 6 V INT, SCK, SI VSS 0.25 VDD
VIL (4) Output n-channel transistors off VDD = 2.5 to 6 V INT, SCK, SI VSS 0.15 VDD
VIL (5) External clock specifications VDD = 4 to 6 V OSC1 VSS 0.25 VDD V
Low-level input voltage
VIL (6) External clock specifications VDD = 2.5 to 6 V OSC1 VSS 0.15 VDD
VIL (7) VDD = 4 to 6 V TEST VSS 0.3 VDD
VIL (8) VDD = 2.5 to 6 V TEST VSS 0.2 VDD
VIL (9) VDD = 4 to 6 V RES VSS 0.25 VDD
VIL (10) VDD = 2.5 to 6 V RES VSS 0.15 VDD
Operating frequency 200 4330
fop (Tcyc) kHz (µs)
(cycle time) (20) (0.92)
External clock conditions
Frequency text OSC1 200 4330 kHz
Pulse width textH, textL Figure 1. OSC1 69 ns
Rise and fall times textR, textF OSC1 50 ns
Recommended oscillator
circuit constants Figure 2 See table 1.
Ceramic oscillator *4

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
• Output n-channel transistors off
Ports C, D, E and F with
(Including the n-channel transistor
IIH (1) the open-drain 5.0
off leakage current.)
specifications
• VIN = 13.5 V
• Output n-channel transistors off
High-level input current
(Including the n-channel transistor Ports A and G with the µA
IIH (2) 1.0
off leakage current.) open-drain specifications
• VIN = VDD
IIH (3) When an external clock is used,
OSC1 1.0
VIN = VDD
• Output n-channel transistors off Ports with the open-drain
IIL (1) –1.0
• VIN = VSS specifications
• Output n-channel transistors off Ports with the pull-up
IIL (2) –1.3 –0.35 mA
Low-level input current • VIN = VSS resistor specifications
IIL (3) VIN = VSS RES –45 –10
When an external clock is used, µA
IIL (4) OSC1 –1.0
VIN = VSS
• IOH = –50 µA Ports with the pull-up
VOH (1) VDD – 1.2
• VDD = 4.0 to 6.0 V resistor specifications
High-level output voltage
Ports with the pull-up
VOH (2) IOH = –10 µA VDD – 0.5
resistor specifications
• IOL = 10 mA
VOL (1) Port 1.5
• VDD = 4.0 to 6.0 V
Low-level output voltage
When IOL = 1 mA and the IOL for V
VOL (2) Port 0.5
each port is 1 mA or less.
Schmitt characteristics

Hysteresis voltage VHIS 0.1 VDD

RES, INT, SCK, SI, and
High-level threshold
VtH OSC1 with Schmitt 0.4 VDD 0.8 VDD
voltage specifications*5
Low-level threshold
VtL 0.25 VDD 0.6 VDD
voltage
Continued on next page.

No. 6278-22/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Current drain*6
IDDOP (1) • Figure 2, 4 MHz VDD 2 6
• 200 kHz to 4330 kHz
mA
Ceramic oscillator • Operating, with the output
IDDOP (2) n-channel transistors off and the VDD 2 6
ports at VDD.
• Output n-channel transistors off VDD 0.05 10
Standby mode IDDst VDD = 6 V µA
• Ports at VDD, VDD = 2.5 V VDD 0.025 5

Oscillator characteristics
fCFOSC*7 • Figure 2, fo = 4 MHz OSC1, OSC2 3920 4000 4080 kHz
Ceramic oscillator
Oscillator frequency*8 tCFS • Figure 3, fo = 4 MHz 10 ms
Pull-up resistor • Output n-channel transistors off Pull-up resistor
RPP 8 14 30
I/O ports • VIN = VSS, VDD = 5 V specification ports kΩ
RES Ru VIN = VSS, VDD = 5 V RES 200 500 800
External reset characteristics
tRST See figure 4.
Reset time
• f = 1 MHz
Pin capacitances Cp • With all pins other than the pin 10 pF
being tested at VIN = VSS.
Serial clock
tCKCY (1) Figure 5 SCK 2.0
Input clock cycle time
Output clock cycle time tCKCY (2) Figure 5 SCK 64 × TCYC*9
Input clock low-level pulse
tCKL (1) Figure 5 SCK 0.6
width
Output clock low-level pulse
tCKL (2) Figure 5 SCK 32 × TCYC
width
Input clock high-level pulse
tCKH (1) Figure 5 SCK 0.6
width
Output clock high-level
tCKH (2) Figure 5 SCK 32 × TCYC
pulse width
Serial input
Data setup time tICK • Stipulated with respect to the SI 0.2
rising edge of SCK. µs
• Figure 5
Data hold time tCKI SI 0.2
Serial output • Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
SO 0.4
Output delay time tCKO and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
• Figure 5
Pulse output function
Period tPCY • Figure 6 PE0 64 × TCYC
• TCYC = 4 × system clock
period
High-level pulse width tPH • With an external resistor of PE0 32 × TCYC
1 kΩ and an external ±10%
capacitor of 50 pF on only
the n-channel open-drain 32 × TCYC
Low-level pulse width tPL PE0
pins. ±10%

Continued on next page.

No. 6278-23/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
Resolution VDD = 3 to 6 V 8 bit
AV+ = VDD A/D converter speed 1/1 VDD = 3.5 to 6 V ±1 ±2
Absolute precision LSB
AV– = VSS A/D converter speed 1/2 VDD = 3.5 to 6 V ±1 ±2
When the A/D converter 24 312
speed is normal (1/1), VDD = 3.5 to 6 V (TCYC = (TCYC =
namely 26 × TCYC 0.92 µs) 12 µs)
Conversion time TCAD µs
A/D converter characteristics

When the A/D converter 47 612

speed is one half (1/2), VDD = 3 to 6 V (TCYC = (TCYC =
namely 51 × TCYC 0.92 µs) 12 µs)
AV+ AV+ AV– VDD
Input reference voltage V
AV– AV– VSS AV+
Input reference current
IRIF AV+ = VDD, AV– = VSS AV+, AV– 200 500 800 µA
range
Analog input voltage
VAIN AD0 to AD7 AV– AV+ V
range
VDD = 3 to 6 V
Including the output off AD0 to AD7
leakage current. (The I/O 1
VAIN = VDD shared
Analog port input current IAIN function ports µA
have open-
VAIN = VSS –1
drain
specifications.)
When PE1 has the
Cw WDR 0.01 ±5% µF
open drain specifications.
Watchdog timer

Recommended When PE1 has the

Rw WDR 680 ±1% kΩ
constants*10 open drain specifications.
When PE1 has the
RI WDR 100 ±1% Ω
open drain specifications.
Clear time (discharge) tWCT Figure 7 WDR 10 µs
Clear period (charge) tWCCY Figure 7 WDR 4.2 ms

Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 2 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 3).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.

No. 6278-24/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

External clock open

Figure 1 External Clock Input Waveform

Ceramic oscillator
element

Figure 2 Ceramic Oscillator Circuit

No. 6278-25/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Lower limit for the operating supply voltage

Stable oscillation
Oscillation
stabilization
time tCFS

Figure 4 Oscillation Stabilization Time

Table 1 Recommended Ceramic Oscillator Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MG C2 33 pF ±10%
CST4.00MGW (Internal capacitor) R 0Ω
4 MHz (Kyocera Corporation) C1 33 pF ±10%
KBR4.0MSA C2 33 pF ±10%
KBR4.0MKS (Internal capacitor) R 0Ω

Figure 5 Reset Circuit

Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.

No. 6278-26/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Input data
Load circuit

Output data

Figure 5 Serial I/O Timing

The load conditions are the same

as those in figure 4.

Figure 6 Port PE0 Pulse Output Timing

tWCCY: The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT: The discharge time due to software processing.

Figure 7 Watchdog Timer Waveform

No. 6278-27/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

LC651154L, 651152L

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter Symbol Conditions Applicable pins and notes Ratings Unit
Maximum supply voltage VDD max VDD –0.3 to +7.0
Allowed up to the
Output voltage VO OSC2
generated voltage.
VI (1) OSC1 *1 –0.3 to VDD + 0.3
Input voltage V
VI (2) TEST, RES, AV+, AV– –0.3 to VDD + 0.3
VIO (1) PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports –0.3 to +15
I/O voltage VIO (2) PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports –0.3 to VDD + 0.3
VIO (3) PA0 to PA3, PG0 to PG3 –0.3 VDD + 0.3
Peak output current IOP I/O ports –2 to +20
IOA Per single pin, averaged over 100 ms I/O ports –2 to +20
PC0 to PC3
The total current for PC0 to PC3,
∑IOA (1) PD0 to PD3 –15 to +100
PD0 to PD3, and PE0 to PE1 *2 mA
Average output current PE0 to PE1
PF0 to PF3
The total current for PF0 to PF3, PG0 to PG3,
∑IOA (2) PG0 to PG3 –15 to +100
and PA0 to PA3 (See note 2.) *2
PA0 to PA3
Pd max (1) Ta = –40 to +85°C (DIP package) 310
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package) 220 mW
Pd max (3) Ta = –40 to +85°C (SSOP package) 160
Operating temperature Topr –40 to +85
°C
Storage temperature Tstg –55 to +125

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Operating supply voltage VDD VDD 2.2 6.0
Standby supply voltage VST RAM and register values retained*3 VDD 1.8 6.0
Ports C, D, E, and F with
VIH (1) Output n-channel transistors off 0.7 VDD 13.5
open-drain specifications
Ports C, D, E, and F with
VIH (2) Output n-channel transistors off 0.7 VDD VDD
pull-up resistor specifications
VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD
The INT, SCK, and SI
High-level input voltage VIH (4) Output n-channel transistors off pins with open-drain 0.8 VDD 13.5
specifications
The INT, SCK, and SI V
VIH (5) Output n-channel transistors off pins with pull-up resistor 0.8 VDD VDD
specifications
VIH (6) VDD = 1.8 to 6.0 V RES 0.8 VDD VDD
VIH (7) External clock specifications OSC1 0.8 VDD VDD
VIL (1) Output n-channel transistors off Port VSS 0.2 VDD
VIL (2) Output n-channel transistors off INT, SCK, SI VSS 0.15 VDD
Low-level input voltage VIL (3) Output n-channel transistors off OSC1 VSS 0.15 VDD
VIL (4) TEST VSS 0.2 VDD
VIL (5) RES VSS 0.15 VDD

Continued on next page.

No. 6278-28/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
The clock may have a frequency up to
Operating frequency 200 1040
fop (Tcyc) 4.16 MHz when the divide-by-four internal kHz (µs)
(cycle time) (20) (3.84)
divider circuit option is used.
External clock conditions Figure 1.
Frequency text Either the divide-by-three or divide-by- OSC1 200 4160 kHz
Pulse width textH, textL four internal divider circuit must be used if OSC1 100 ns
the clock frequency exceeds 1.040 MHz.
Rise and fall times textR, textF OSC1 100 ns
Recommended oscillator
circuit constants
Two-pin RC oscillator Cext Figure 2 OSC1, OSC2 270 ±5% pF
Rext 12 ±1% kΩ
Ceramic oscillator *4 Figure 3 See table 1.

No. 6278-29/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
• Output n-channel transistors off
Ports C, D, E and F with
(Including the n-channel transistor
IIH (1) the open-drain 5.0
off leakage current.)
specifications
• VIN = 13.5 V
• Output n-channel transistors off
High-level input current
(Including the n-channel transistor Ports A and G with the µA
IIH (2) 1.0
off leakage current.) open-drain specifications
• VIN = VDD
IIH (3) When an external clock is used,
OSC1 1.0
VIN = VDD
• Output n-channel transistors off Ports with the open-drain
IIL (1) –1.0
• VIN = VSS specifications
• Output n-channel transistors off Ports with the pull-up
IIL (2) –1.3 –0.35 mA
Low-level input current • VIN = VSS resistor specifications
IIL (3) VIN = VSS RES –45 –10 µA
When an external clock is used, OSC1 –1.0
IIL (4)
VIN = VSS
Ports with the pull-up
High-level output voltage VOH • IOH = –10 µA VDD – 0.5
resistor specifications
VOL (1) • IOL = 3 mA Port 1.5
Low-level output voltage When IOL = 1 mA and the IOL for V
VOL (2) Port 0.4
each port is 1 mA or less.
Schmitt characteristics

Hysteresis voltage VHIS 0.1 VDD

RES, INT, SCK, SI, and
High-level threshold
VtH OSC1 with Schmitt 0.4 VDD 0.8 VDD
voltage specifications*5
Low-level threshold
VtL 0.2 VDD 0.6 VDD
voltage
Current drain *6 • Operating, with the output
n-channel transistors off
Two-pin RC oscillator IDDOP (1) VDD 1.0 4
• With the ports at VDD
• Figure 2, fosc = 800 kHz (typical)
Ceramic oscillator IDDOP (2) • Figure 3, 4 MHz, divide-by-four circuit used VDD 1.5 4
• Figure 3, 4 MHz, divide-by-four circuit used
IDDOP (3) VDD 0.5 1
VDD = 2.2 V
IDDOP (4) • Figure 3, 400 kHz VDD 1.0 2.5 mA
IDDOP (5) • Figure 3, 800 kHz VDD 1.5 4
• 200 kHz to 1024 kHz, no divider
circuit
• 600 kHz to 3120 kHz, divide-by-
External clock IDDOP (6) three circuit used VDD 1.5 4
• 800 kHz to 4160 kHz, divide-by-
four circuit used
Output n-channel transistors off, VDD 0.05 10
Standby mode IDDst VDD = 6 V µA
Ports at VDD, VDD = 2.2 V VDD 0.020 4

Continued on next page.

No. 6278-30/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins and notes Unit
min typ max
Oscillator characteristics • Figure 3, fo = 400 kHz OSC1, OSC2 392 400 408
• Figure 3, fo = 800 kHz OSC1, OSC2 784 800 816
Ceramic oscillator • Figure 3, fo = 1 MHz OSC1, OSC2 980 1000 1020
Oscillator frequency fCFOSC*7 kHz
• Figure 3, fo = 4 MHz, with the OSC1, OSC2 3920 4000 4080
divide-by-four
circuit used.
• Figure 4, fo = 400 kHz 10
Oscillator stabilization time *8 • Figure 4, fo = 800 kHz, 1 MHz, or 10
tCFS ms
4 MHz, with the divide-by-four
circuit used.
Two-pin RC oscillator • Figure 2, Cext = 270 pF ±5%
fMOSC OSC1, OSC2 290 400 841 kHz
Oscillator frequency • Figure 2, Rext = 5.6 kΩ ±1%
Pull-up resistor • Output n-channel transistors off Pull-up resistor
RPP 8 14 30
I/O ports • VIN = VSS, VDD = 5 V specification ports kΩ
RES Ru VIN = VSS, VDD = 5 V RES 200 500 800
External reset characteristics
tRST See figure 5.
Reset time
• f = 1 MHz
Pin capacitances Cp • With all pins other than the pin 10 pF
being tested at VIN = VSS.
Serial clock
Input clock cycle time tCKCY (1) Figure 6 SCK 2.0

Output clock cycle time tCKCY (2) Figure 6 SCK 64 × TCYC*9

Input clock low-level pulse
tCKL (1) Figure 6 SCK 2.0
width
Output clock low-level pulse
tCKL (2) Figure 6 SCK 32 × TCYC
width
Input clock high-level pulse
tCKH (1) Figure 6 SCK 2.0
width
Output clock high-level
tCKH (2) Figure 6 SCK 32 × TCYC
pulse width
Serial input

Data setup time tICK • Stipulated with respect to the SI 0.5

rising edge of SCK. µs
• Figure 6
Data hold time tCKI SI 0.5
Serial output • Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
SO 1.0
Output delay time tCKO and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
• Figure 6
Pulse output function
• Figure 7
Period tPCY • TCYC = 4 × system clock PE0 64 × TCYC
period
• With an external resistor of
High-level pulse width tPH 1 kΩ and an external PE0 32 × TCYC
capacitor of 50 pF on only ±10%
the n-channel open-drain
32 × TCYC
Low-level pulse width tPL pins. PE0
±10%

Continued on next page.

No. 6278-31/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins Unit
and notes min typ max
Resolution 8 bit
AV+ = VDD ±1 ±2 LSB
Absolute precision
AV– = VSS
When the A/D converter 99 312 µs
speed is normal (1/1), (TCYC = (TCYC =
namely 26 × TCYC 3.84 µs) 12 µs)
Conversion time TCAD
When the A/D converter 195 612
A/D converter characteristics

speed is one half (1/2), (TCYC = (TCYC =

namely 51 × TCYC 3.84 µs) 12 µs)
AV+ AV+ AV– VDD
Input reference voltage V
AV– VDD = 3 to 6 V AV– VSS AV+
Input reference current AV+ = VDD
IRIF AV+, AV– 200 500 800 µA
range AV– = VSS
Analog input voltage
VAIN AD0 to AD7 AV– AV+ V
range
Including the output off AD0 to AD7
leakage current. (The I/O 1
VAIN = VDD shared
Analog port input current IAIN function ports µA
have open-
VAIN = VSS –1
drain
specifications.)
When PE1 has the
Cw WDR 0.1 ±5% µF
open-drain specifications.
Recommended When PE1 has the
Rw WDR 680 ±1% kΩ
constants*10 open-drain specifications.
VDD = 2.2 to 6 V
When PE1 has the
RI WDR 100 ±1% Ω
open-drain specifications.
Watchdog timer

Clear time (discharge) tWCT Figure 8 WDR 100 µs

Clear period (charge) tWCCY Figure 8 WDR 31 ms
When PE1 has the
Cw WDR 0.047 ±5% µF
open-drain specifications.
Recommended When PE1 has the
Rw WDR 680 ±1% kΩ
constants*10 open-drain specifications.
VDD = 2.2 to 6 V
When PE1 has the
RI WDR 100 ±1% Ω
open-drain specifications.
Clear time (discharge) tWCT Figure 8 WDR 40 µs
Clear period (charge) tWCCY Figure 8 WDR 14 ms

Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 4).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.

No. 6278-32/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

External clock open

0.15 VDD

Figure 1 External Clock Input Waveform

Ceramic oscillator
element

Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit

No. 6278-33/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Lower limit for the operating supply voltage

Stable oscillation
Oscillation
stabilization
time tCFS

Figure 4 Oscillation Stabilization Time

Table 1 Recommended Ceramic Oscillator Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MG C2 33 pF ±10%
CST4.00MGW (Internal capacitor) R 0Ω
4 MHz (Kyocera Corporation) C1 33 pF ±10%
KBR4.0MSA C2 33 pF ±10%
KBR4.0MKS (Internal capacitor) R 0Ω
1 MHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10%
CSB1000J C2 100 pF ±10%
R 3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10% Figure 5 Reset Circuit
CSB800J C2 100 pF ±10%
R 3.3 kΩ
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
400 kHz (Murata Mfg. Co., Ltd.) C1 220 pF ±10% will be between 10 and 100 ms.
CSB400P C2 220 pF ±10% If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
R 3.3 kΩ

No. 6278-34/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Input data
Load circuit

Output data

Figure 6 Serial I/O Timing

The load conditions are the same

as those in figure 5.

Figure 7 Port PE0 Pulse Output Timing

tWCCY: The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT: The discharge time due to software processing.

Figure 8 Watchdog Timer Waveform

No. 6278-35/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

RC Oscillator Characteristics for the LC651154L and LC651152L

Figure 9 shows the RC oscillator characteristics for the LC651154L and LC651152L.
However, the sample-to-sample variation in the LC651154L and LC651152L RC oscillator frequency described below
does occur.
1) When:
VDD = 2.2 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
fMOSC will be:
290 kHz ≤ fMOSC ≤ 841 kHz
Therefore, only the above circuit constants are recommended.

If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)

Note 8. The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25°C.
Note 9. Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range VDD = 2.2 to 6.0 V and for
the temperature range Ta = –40 to 85°C.

These characteristics curves are for

reference purposes only and are not
guaranteed.

Figure 9 RC Oscillator Frequency Data (Representative Values)

No. 6278-36/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Notes on Printed Circuit Board Design

This section describes points that require care concerning noise from the point of view of the microcontroller and
presents means of preventing associated problems when designing a printed circuit board to use with these products in a
mass produced end product. The ideas presented in this section are effective design techniques for preventing and
avoiding problems (such as incorrect microcontroller operation and program failures) due to noise.
1. The VDD and VSS power supply pins
Insert capacitors that meet the following conditions between the VDD and VSS power supply pins.
• The lengths of the lines between the VDD and VSS pins and the capacitors C1 and C2 should be as close to exactly
equal as possible (L1 = L1’, L2 = L2’). Furthermore, these distances should be as short as possible.
• Insert two capacitors, C1 and C2 in parallel, with C1 having a large capacitance and C2 having a small capacitance.
• The VDD and VSS lines in the printed circuit board pattern should be wider than any other lines in the pattern.

2. The OSC1 and OSC2 clock I/O pins

— If the ceramic oscillator option is selected (See figure 2-1.)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components as short as possible (the
distance Losc in the figure).
• Make the length of the lines (Lvss + L1 and Lvss + L2) from
the microcontroller VSS pin to the VSS side of the capacitors
connected to the oscillator element as short as possible.
• VSS line for the oscillator circuit and other VSS line should
branch from a point nearest to the VSS pin.
• Due to the capacitances of the wiring on the printed circuit
board, it may be necessary to modify the values of the oscillator
circuit constants (including the values of the capacitors C1 and Figure 2-1 Sample Oscillator Circuit 1
C2 and the limiting resistor Rd) from the values presented in (Ceramic oscillator)
this catalog. We recommend consulting the manufacturer of the
oscillator element with regard to these circuit constants.
— If the 2-pin RC oscillator option is selected (Figure 2-2)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components (the capacitor Cext and the
resistor Rext) as short as possible (the distance Losc in the figure).
• Make the length of the lines (Lvss + Lc) from the
microcontroller V SS pin to the V SS side of the capacitor
functioning as the oscillator element as short as possible.
• Take the VSS used by the oscillator circuit (as well as other VSS
usages) from a point as close as possible to the VSS pin.
— If the external oscillator option is selected (Figure 2-3) Figure 2-2 Sample Oscillator Circuit 2
• Keep the line between the clock input pin (OSC1) and the external (2-pin RC oscillator)
oscillator circuit as short as possible (the distance Losc in the figure).
• Leave the clock output pin (OSC2) open.
• Make the length (Losc) of the lines to the VDD and VSS pins
used by the external oscillator as short as possible.
— Other points that apply to all oscillator circuits:
• Keep all lines that carry signals that change rapidly, signals that External
oscillator
have large amplitudes due to being connected to the medium-
voltage handling capacity ports, or signals that carry large
currents as far away from the oscillator circuit as possible. Also,
do not allow such signal lines to cross any clock-signal related
lines.
Figure 2-3 Sample Oscillator Circuit 3
(External oscillator)

No. 6278-37/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

3. RES: Reset pin

• Keep the length of lines (Lres in the figure) from the RES pin to external circuits as short as possible.
• Keep the length of the lines (L1 and L2) to the capacitor (Cres) inserted between RES and VSS as short as possible.

External
circuit

Figure 3 RES Pin Wiring

4. TEST: Test pin

• Keep the length of the line (L) from the TEST pin to the VSS pin as short as possible.
• Run the line from the TEST pin to the VSS pin as close to the VSS pin as possible.

Figure 4 TEST Pin Wiring

5. AD0 to AD7: Analog input pins

Analog input pin lines, such as those used to connect to an A/D converter input pin or a comparator input pin should
be connected so as to meet the following conditions.
• Keep the line (L1) between the limiting resistor (Rl) and the analog input pin as short as possible.
• Locate the capacitor inserted between the analog input pins and the AV- pin (the A/D converter reference voltage
input pin) as close as possible to the AV- input pin. That is, make the line length L1 + L2 as short as possible.

Analog
input pin

External circuit
(sensor block)

Figure 5 Analog Input Pin Wiring

6. I/O pins
All of the pins on these products function as both input and output pins.
• When used as an input pin, insert a limiting resistor, and keep the length of the line to that pin as short as possible.
Supplement: This is not only useful in printed circuit board design, but is also useful in preventing and avoiding
problems (such as incorrect microcontroller operation and program failures) by taking the program specifications
and microcontroller option selections described below into consideration.
• If signals are input from external sources when the microcontroller power supply is unstable, select the medium-
voltage handling capacity (n-channel open drain) output as the output type option for that input pin, and also insert
a limiting resistor in the input circuit.
• Always implement key chattering exclusion measures for external signals applied to microcontroller input pins.
• The pin output data should be re-output periodically with an output instruction (OP or SPB).

No. 6278-38/39
 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

• When reading data input to a pin that can function as either input or output, set the output value for that pin to 1
every time the input is read using an output instruction (OP or SPB).
7. Unused pins
• See the users manual for the product or refer to the pin functions as described in the semiconductor report for the
device.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of September, 1999. Specifications and information herein are
subject to change without notice.

PS No. 6278-39/39
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.