Verilog Tutorial For Beginner's
Verilog Tutorial For Beginner's
Verilog Tutorial For Beginner's
HDL
Verilog
Taste of Verilog
Module name
Module ports
Declaration of internal
signal
Instantiation of primitive
gates
a
b
G1
sum
c_out_bar
c_out
Lexical Convention
Lexical Convention
b(binary),d(decimal),o(octal),h(hex).
Lexical Convention
Example :
347 // decimal number
4b101 // 4- bit binary number 0101
2o12 // 2-bit octal number
5h87f7 // 5-bit hex number h87f7
2d83 // 2-bit decimal number
Lexical Convention
Program structure
Structure
module <module name> (< port list>);
< declares>
<module items>
endmodule
. Module name
an identifier that uniquely names the module.
. Port list
a list of input, inout and output ports which are
referenced in other modules.
Program structure
. Declares
section specifies data objects as registers,
memories and wires as well as procedural constructs
such as functions and tasks.
. Module items
initial constructs
always constructs
assignment
endmodule
Dataflow modeling
Behavioral modeling
Structural model
//structural model of a NAND gate
// program nand2.v
module my_NAND(A, B, F);
input A, B;
output F;
nand G(F, A, B); // first parameter must be output.
endmodule
Structural Modeling
//Gate-level description of a 2-to-4-line decoder
//Figure 4-19
module decoder_gl (input A,B,E, output [0:3] D);
wire Anot, Bnot, Enot;
not
n1 (Anot, A),
n2 (Bnot, B),
n3 (Enot, E);
nand
n4 (D[0], Anot, Bnot, Enot),
n5 (D[1], Anot,B, Enot),
n6 (D[2], A, Bnot, Enot),
n7 (D[3], A, B, Enot);
endmodule
Dataflow Modeling
//HDL Example 4-3
//---------------------------------------------//Dataflow description of a 2-to-4-line decoder
//See Fig.4-19
module decoder_df (output [0:3] D, input A, B,
enable);
assign D[0] = ~(~A & ~B & ~ enable),
D[1] = ~(~A & B & ~ enable),
D[2] = ~(A & ~B & ~ enable),
D[3] = ~(A & B & ~ enable);
endmodule
Dataflow Modeling
//HDL Example 4-4
//---------------------------------------//Dataflow description of 4-bit adder
module binary_adder (A, B, Cin, SUM, Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout, SUM} = A + B + Cin;
endmodule
concatenation
Binary addition
Dataflow Modeling
//HDL Example 4-5
//----------------------------------//Dataflow description of a 4-bit comparator.
module magcomp (A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B),
AGTB = (A > B),
AEQB = (A == B);
endmodule
Dataflow Modeling
//HDL Example 4-6
//---------------------------------------//Dataflow description of 2-to-1-line multiplexer
module mux2x1_df (A, B, select, OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
Behavioral Description
module Add_half ( sum, c_out, a, b );
input
a, b;
a
output
sum, c_out;
b
reg sum, c_out;
always @ ( a or b )
begin
sum = a ^ b;
// Exclusive or
c_out = a & b;
// And
end
endmodule
Must be of the
reg type
Add_half
Procedure
assignment
statements
sum
c_out
Event control
expression
Example of Flip-flop
module Flip_flop ( q, data_in, clk, rst );
input
data_in, clk, rst;
output
q;
reg q;
always @ ( posedge clk )
begin
if ( rst == 1) q = 0;
else q = data_in;
end
endmodule
rst
data_in
clk
Procedural statement
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