IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO.

7, JULY 2011 2883

Design of Robust Digital PID Controller for
H-Bridge Soft-Switching Boost Converter
Veerachary Mummadi
AbstractIn this paper, a robust digital proportionalintegral
derivative (PID) controller is proposed for the H-bridge soft-
switching boost converter (HSBC). This digital PID controller is
designed to ensure load voltage regulation as well as to give robust
performance with step loads and source rejection. The mathemat-
ical models of the H-bridge boost converter are formulated, using
the system identication tool, and then used in digital PID design.
Here, this compensator is designed in the direct digital domain ac-
cording to a pole placement approach that uses sensitivity function
shaping in order to ensure closed-loop converter system stability
as well as robust performance against converter parameter uncer-
tainties. To conrm this, design simulations have been carried out
on a 60-W 2442-V HSBC. The experimental results are provided
to validate the robust controller design concept.
Index TermsDigital proportionalintegralderivative (PID)
controller, H-bridge soft-switching converter, robust performance,
sensitivity functions.
I. INTRODUCTION
H
IGH-FREQUENCY switching converter applications in
low-power compact electronic circuits have increased in
recent years. As power conversion systems become miniatur-
ized, increasing the power density is one of the challenging is-
sues for power supply designers. One of the main orientations in
power electronics in the last decade has been the development
of switching-mode converters with a higher power density and
low electromagnetic interference. Low weight, small size, and
high power density are also some of the key design parameters
[1][3]. The need to increase the power density is related to
converter design and packaging. Conventional boost converter-
based topologies are well established for applications requiring
higher load voltages. However, hard switching results in a
considerable amount of power loss and imposes a constraint
on the maximum achievable efciency. In order to reduce
the switching losses and realize higher efciencies, several
soft-switching (SFSW) techniques have been reported in the
literature [4][13]. Some of these topologies are accompanied
by higher voltage, higher current stress, and larger conduc-
tion losses than those in hard-switched pulsewidth modulated
(PWM) converters. Zero-voltage switching is realized with a
switched snubber in [6]. Zero-voltage/zero-current switching
Manuscript received April 25, 2010; revised July 27, 2010; accepted
August 28, 2010. Date of publication September 20, 2010; date of current
version June 15, 2011.
The author is with the Department of Electrical Engineering, Indian Institute
of Technology Delhi, New Delhi 110016, India (e-mail: [email protected].
ac.in).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIE.2010.2077615
PWM converters are reported in [11]. However, these solu-
tions need additional drive circuitry. Although quasi-resonant
converters are capable of achieving higher efciencies, they
must be operated at variable switching frequencies. Further-
more, optimizing resonant tank elements for such converters
is a tedious task. Single-switch SFSW converters have also
resulted in higher efciencies, but they exhibit higher voltage
and current stresses. An H-bridge-based soft-switching scheme
was introduced for conventional buck, boost, and buckboost
converters [13]. This concept used an auxiliary switch, a pair
of diodes, and the main switch-forming bridge network. The
analysis of a soft-switching boost converter topology with a
zero-voltage turn-on feature is reported in the literature. How-
ever, there is insufcient literature covering the development
of controllers for such kinds of converters. In order to bridge
this gap, this paper presents investigations on robust digital
proportionalintegralderivative (PID) controller design with
the following features: 1) ensures load voltage regulation;
2) rejects source and load disturbances; and 3) rejects converter
parameter variation.
Although custom-built IC-based analog controllers are well
established for switched-mode power supplies (SMPSs) [1]
[3], digital controllers offer many advantages over their analog
counterparts. Due to recent advances in microcontrollers/digital
signal processors, there has been a growing interest in the
application of digital controllers for high-frequency conversion
systems and low- to medium-power dcdc converters due to
the low price-to-performance ratio for implementing complex
control strategies [14][23]. Several compensator design ap-
proaches have been reported in the literature for operational-
amplier or IC-based analog controllers. However, in the case
of digital controller design [15], the following two main ap-
proaches are widely used: 1) digital redesign method (DRM)
and 2) direct digital design method (DDDM). In the rst
case, the compensator is designed in the conventional way
by using s-domain transfer functions, together with a linear
system theory, and the resulting compensator is transformed
into the digital domain using appropriate z-transformations.
The main limitations of the DRM are the following: 1) The
discretized controller is not guaranteed to have closed-loop
system (CLS) stability; 2) CLS properties need to be taken
into account while choosing a particular discretization method;
3) for a given converter, the selection of the discretization
method depends on the sampling rate at which the digital con-
troller needs to be operated; and 4) the sampling rate, together
with the selection of the discretization method, gives many
digital controller congurations, and some of these controllers
will not stabilize the actual closed-loop converter. Furthermore,
0278-0046/$26.00 2010 IEEE
2884 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
Fig. 1. Circuit diagram of HSBC.
such designs need a lot of tuning of the gain parameters before
they are operational. On the other hand, in the DDDM, the
compensator design is carried out in the z-domain itself, and
hence, there is no need for s-to-z-domain transformation. Since
the DDDM handles discrete-transfer functions, in their design,
it is possible to include the sample-and-hold time-delay effects,
if there are any, and thus, the nal resulting digital controller is
more realistic and meets the design tradeoffs without needing
any ne tuning.
Controllers, whether analog or digital, are more sensitive
to noise, parameter variation, and external disturbances. In
order to make a digital controller that is capable of rejecting
disturbances and is more immune to perturbations, which may
be either internal or external, the controller must be designed
while taking extreme operating conditions into account. In this
context/direction, robust control methods [24][30] are more
common in the design of conventional controllers; however,
their application in the digital controller domain is slowly
becoming more common. The purpose of these investigations
is to design a robust digital PID design for an H-bridge soft-
switching boost converter (HSBC), and a detailed discussion is
given in the following sections.
II. ANALYSIS AND DISCRETE-TIME
MODEL FORMULATION OF HSBC
An HSBC is shown in Fig. 1. Compared to the conventional
boost converter, it has an additional soft-switching network
which is indicated within the box and consists of two diodes
(D
1
, D
2
), an auxiliary switch (S
a
), a capacitor (C
r
), and an
inductor (L
r
). This HSBC operates in six different operating
modes [13] in one PWM cycle, and the conducting devices
in each mode of operation are as follows: 1) mode-1: D-ON;
2) mode-2: S
m
, S
a
, and D are in the ON-state; 3) mode-3: S
m
and S
a
are in the ON-state while L
r
and C
r
are resonating;
4) mode-4: S
m
, S
a
, D
1
, and D
2
are in the ON-state; 5) mode-5:
D
1
and D
2
are in the ON-state while L
r
and C
r
are resonating;
6) mode-6: D
1
, D
2
, and D are in the ON-state. The steady-state
voltage gain of this HSBC has an identical form, V
0
= V
g
/(1
D
e
), to that of the conventional boost converter, except that it
uses an effective duty ratio D
e
= (D D), where D is
the duty ratio loss due to the soft switching.
Generalized state-space averaging (GSSA) is one of the well-
established techniques employed for modeling soft-switching
PWM dcdc converters [35]. However, this model formulation
TABLE I
HSBC PARAMETERS
methodology assumes variables associated with the resonant
tank (L
r
, C
r
) as input control variables, rather than as state
variables. In view of this, the resulting model accuracy is low.
To improve the model accuracy, a larger number of harmonics
need to be included in the GSSA model. This increases the
order of the model, and its mathematical analysis now becomes
much more complex. To alleviate some of these problems,
system identication techniques have been reported in the
literature for modeling switch-mode dcdc converters [36]
[38]. The advantages of these techniques are as follows: 1) The
internal structure of the converter need not be known in advance
as long as one can obtain a satisfactory statistical distribution
of the data; 2) in some cases, this approach is very effective
at generating a reduced-order model to represent a complex
subsystem of the distributed power electronic system; and
3) this method is particularly useful in a SMPS where there
are many modes of operation and where there is difculty in
nding the duty ratio of each mode operation, etc.
Although several system identication tools can be em-
ployed for soft-switching converter model formulation, here,
a BoxJenkins [35][39] methodology is used for the HSBC
discrete-transfer function generation. Taking the designed con-
verter parameters, rstly, the HSBC is formulated in a Simulink
platform, and then, the response of the desired parameter is
generated for a given range of perturbation of the predened
parameter. Here, the perturbation range and sampling frequency
of the perturbing signal and the duty ratio play an important
role in the accuracy of the nal transfer functions generated.
Hence (in the converter discrete-transfer function generation),
the control duty ratio range must be chosen judiciously in order
to get accurate transfer functions. For a given source voltage
and load resistance range, shown in Table I, the duty ratio
varies between 0.3 and 0.7, and this is used as the range for the
perturbation duty ratio control signal. Taking these boundaries,
equally spaced intermediate points with a step time equal to the
sampling time period are generated using a random generator.
This signal is then compared with the triangular ramp and used
to generate an equivalent duty ratio signal which is used to drive
the switching device of the converter. Since there is a perturba-
tion in the converter, various current and voltage quantities will
have corresponding variations. In order to nd the converter
discrete-transfer function of interest, the corresponding samples
of current or voltage and the perturbation signals are passed on
to the system identication toolbox of MATLAB [41]. In this
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2885
Fig. 2. Block diagram of the digital PID controlled HSBC.
toolbox, the user has the option to choose a linear parametric
model formulation methodology and its tting order for the
given inputoutput data pattern. Once these are decided, then,
the model is estimated, and its accuracy is veried by residual
analysis. If the residual of the model is within the allowable
condence interval, then the corresponding estimated model
represents the true behavior of the converter. Although it is
possible to establish various discrete-transfer functions for the
HSBC, only the transfer functions which are useful for robust
controller design are estimated and then used in the controller
design.
For a given load power demand, source, and load voltages,
the power stage parameters L and C are designed such that the
inductor current ripple is less than 20% of the load current and
the load voltage ripple is less than 5% of the load voltage using
the following design equations: L = D(1 D)
2
RI
0
/(f
s
I
L
)
and C = (1 D)V
0
/(Rf
s
V
0
). The resonant tank circuit is
designed such that its time constant is ve times lower than the
power stage time constant as per the design procedure discussed
in [13], and the corresponding design equations are as follows:
L
r
= Z
r
/
r
and C
r
= 1/(Z
r

r
).
III. RPIDC DESIGN FOR THE HSBC
A. Digital PID Controller Design Through Pole Placement
Fig. 2 shows the digitally controlled HSBCsystem, where the
loop gain is dened by T
L
(z
1
) = G
cr
(z
1
)G
vd
(z
1
). Here,
we need to design a robust digital PID controller (RPIDC)
G
cr
(z
1
) such that the load voltage is constant irrespective of
the uncertainties in the converter parameters, the disturbances
caused by the input dc bus, or load uctuations. The selec-
tion of the compensator is more important, and its structure
depends on the order of the converter system. The converter
under consideration is the second order, and hence, simple
compensators, like one-zeroone-pole or one-poletwo-zero
designs, will not be suitable as they will not provide a sufcient
gain margin (GM) or phase margin (PM). The option left to
the designer is a high-order compensator: a minimum of two
zeros and two poles. Several other types of higher-order digital
compensators [29] can easily be designed for this converter, but
for the sake of simplicity, both from the point of view of the
design and implementation, the second-order compensator with
a two-pole and two-zero conguration is sufcient in order to
realize the performance tradeoffs. Although this compensator
is simple to implement, the judicious selection of the pole-zero
(PZ) location is required to meet the robustness performance
specications [30][34]. A digital PID controller, of a three-
branch-structured RST controller shown in Fig. 2, is designed
in this paper in order to ensure load voltage regulation and
robustness against converter parameter uncertainty as well as
step source and load rejection. Using the well-known pole-
placement technique (PPT), the RPIDC can easily be designed
for the HSBC. However, such pole-placement design may not
satisfy all the control specications, and hence, the probability
of achieving regulation under all possible operating conditions
of the converter is low. In order to ensure load voltage regula-
tion, together with acceptable robust performance, for a given
class of converter parameter uncertainty, the PPT must be com-
bined with sensitivity function shaping (SFS). Here, SFS gives
additional exibility to obtain a certain performance and to en-
sure some robustness with respect to unstructured uncertainty.
To this effect, here, a design procedure is developed based
on a combination of the PPT and SFS methods such that the
resulting controller meets predened robustness specications.
A block diagram of the closed-loop converter (CLC) is
shown in Fig. 2. The problem here is to design the R-S-T
controller polynomials such that the CLC is stable and robust
against converter parameter uncertainty. Since the goal of these
investigations is to design an RPID, which is equivalent to
a standard R-S-T controller with T = R as shown in Fig. 2,
where the R and S polynomials need to be designed, taking
the robust performance specications into account, let the con-
verter model and controller be dened by the transfer functions
G
vd
(z) and G
cr
(z
1
), respectively, represented in terms of the
numerator and denominator polynomials as
G
vd
(z
1
) =B(z
1
)/A(z
1
) (1a)
G
cr
(z
1
) =R(z
1
)/S(z
1
) (1b)
where B(z
1
) = (b
0
+ b
1
z
1
+ b
2
z
2
), A(z
1
) = (a
0
+
a
1
z
1
+ a
2
z
2
), R(z
1
) = k(1
1
z
1
)(1
2
z
1
) =
[r
0
+ r
1
z
1
+ r
2
z
2
], and S(z
1
) = (1
1
z
1
)(1

2
z
1
) = [q
0
+ q
1
z
1
+ q
2
z
2
], and they do not have any
common factors. The CLC transfer function between the load
voltage and the reference is
H
cl
(z
1
) =
B(z
1
)R(z
1
)
P(z
1
)
(2a)
P(z
1
) =

A(z
1
)S(z
1
) + B(z
1
)R(z
1
)

=P
d
(z
1
)P
a
(z
1
). (2b)
In the PPT, the controller (R, S) is designed such that the CLS
poles are located at the desired locations. Let X
dchp
(z
1
) be
the desired characteristic polynomial (CHP) dened as
X
dchp
(z
1
)=(1
1
z
1
)(1
2
z
1
)(1
3
z
1
)(1
4
z
1
)
=[1+k
1
z
1
+k
2
z
2
+k
3
z
3
+k
4
z
4
] (3)
where k
1
= (
1
+
2
+
3
+
4
), k
4
= (
1

4
), k
2
=
[
1

2
+
3

4
+(
1
+
2
)+(
3
+
4
)], and k
3
= [
1

2
(
3
+
2886 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011

4
)+
3

4
(
1
+
2
)]. Substituting the A(z
1
), B(z
1
), R(z
1
),
and S(z
1
) polynomials in (2b) and comparing with the desired
CHP X
dchp
(z
1
) give a system of four equations with four
unknowns. This system of equations, [M][x] = [], can easily
be solved using matrix inversion, and its equivalent form is
[x] = [M]
1
[] (4)
where
[M] =

a
0
0 b
0
0
a
1
a
2
b
1
b
0
a
2
a
1
b
2
b
1
a
2
0 0 b
2

[x] =

q
1
q
2
r
1
r
2

[] =

(k
1
a
1
q
0
+ b
1
r
0
)
(k
2
a
2
q
0
+ b
2
r
0
)
k
3
k
4

.
From the aforementioned analysis, it is possible to compute
controller parameters G
cr
(z
1
) by placing closed-loop poles
at the desired locations within the unit circle. However, such
a PPT may give a satisfactory xed-point controller but may
not yield robust performance against converter parameter un-
certainty or may exhibit poor dynamic performance in terms of
the step source and load rejection.
In order to achieve load voltage regulation, together with
an acceptable range of robustness, the CLC poles P(z
1
) are
divided into dominant and auxiliary poles. Here, P
d
(z
1
) is
the polynomial corresponding to the CLC dominant poles,
which are chosen to satisfy the desired load voltage regulation
nominal performance. The second polynomial P
a
(z
1
) consists
of the auxiliary poles of the CLC, and their locations must
be chosen judiciously such that the converter system exhibits
acceptably robust performance and is capable of rejecting step
load and source variations. In this context, the sensitivity func-
tions provide a useful means for arriving at a robust controller.
Their shaping, to achieve acceptably robust performance, needs
the rearrangement of poles, depending on the actual converter
nature, type, and range of expected parameter uncertainties.
The detailed description of various sensitivity functions, their
dependence on converter behavior, and robust performance
requirements is discussed in the following paragraphs.
B. Formulation of Sensitivity Functions
The sensitivity functions play a key role in the CLC systems
stability as well as in its robustness performance against
parameter variation. Normally, these functions are shaped
in order to ensure nominal performance for the rejection of
the step load and source disturbances and the stability of
the CLC system in the presence of a model mismatch. The
CLS performance is completely characterized by six different
sensitivity functions. Although these sensitivity functions can
easily be established from the general system analysis point of
view [24], for the regulation of power supplies, the following
sensitivity-indicating transfer functions (STFs) completely
characterize the CLC system stability and robustness: 1) load
Fig. 3. SFG of the digital PID controlled HSBC.
voltage sensitivity against step disturbance dened as output
sensitivity S
yp
; 2) disturbance to control input dened as input
sensitivity S
up
; and 3) measurement noise to output dened as
noise sensitivity S
yb
.
A properly designed dcdc converter has to meet perfor-
mance specications, and these can be readily expressed in
terms of various sensitivity functions. The robustness against
converter parameter variation, either in converter parameters or
in an operating point, is easily captured through the sensitivity
functions, and hence, a design based on the shaping of these
functions results in a realistic controller, which ensures load
voltage regulation, rejects step load and source disturbances,
and is also robust over the specied range of converter parame-
ter variations. The formulation and detailed description of these
sensitivity functions, in the discrete-time domain, for power
supplies are given in the following equations.
S
yp
(z
1
) =
A(z
1
)S(z
1
)
P(z
1
)
(5a)
S
up
(z
1
) =
A(z
1
)R(z
1
)
P(z
1
)
(5b)
S
yb
(z
1
) =
B(z
1
)R(z
1
)
P(z
1
)
. (5c)
A transfer function analysis of the control loop is extremely
useful in identifying clearly the performance objectives of the
controller design problem. Now, let us formulate the mathemat-
ical expressions for the previously dened sensitivity functions
in terms of the converter and controller quantities using the
block diagram shown in Figs. 2 and 3. For a given constant
reference, the load voltage (v
0
) depends on the control input (d)
and disturbing inputs which are the magnitudes of the source
voltage (v
g
) and the load demand (i
0
) on the converter. Without
any closed-loop controller, the load voltage can be written,
from Fig. 3, as
v
0
(z
1
) = G
vg
(z
1
) v
g
(z
1
)
+ Z
0
(z
1
)

i
0
(z
1
) + G
vd
(z
1
)

d(z
1
) (6)
where G
vg
(z
1
)= v
0
(z
1
)/ v
g
(z
1
), Z
0
(z
1
)= v
0
(z
1
)/

i
0
(z
1
),
and G
vd
(z
1
) = v
0
(z
1
)/

d(z
1
). From the signal ow graph
(SFG) shown in Fig. 3, using Masons gain formula, it
is straightforward to establish closed-loop transfer func-
tions v
0
(z
1
)/

d(z
1
)|
v
g
,

i
0
=0
, v
0
(z
1
)/

i
0
(z
1
)|
v
g
,

d=0
, and
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2887
v
0
(z
1
)/ v
g
(z
1
)|

d,

i
0
=0
, and then, the load voltage, due to the
combined effect, is described by
v
0
(z
1
)=S
yp
(z
1
)

G
vg
(z
1
) v
g
(z
1
)+Z
0
(z
1
)

i
0
(z
1
)

(7)
where S
yp
(z
1
)=1/[1+T
L
(z
1
)], T
L
(z
1
)=G
c
(z
1
)G
vd
(z
1
).
The output sensitivity function must be shaped properly in order
to make the load voltage insensitive to the converter parameter
uncertainty, step source, and load perturbations dened by
G
vg
(z
1
), Z
0
(z
1
), and [ v
g
(z
1
) &

i
0
(z
1
)], respectively. The
transfer function that denes the effect of measurement noise
on the load voltage is obtained by setting the perturbing inputs
( v
g
,

i
0
) in Fig. 3 to zero as follows:
v
0
(z
1
) = S
yb
(z
1
)

n(z
1
)

(8)
where S
yb
(z
1
) = T
L
(z
1
)/[1 + T
L
(z
1
)]. In dcdc con-
verter voltage regulation problems, the measured voltage is
superimposed on the switching noise components, and the noise
energy is mostly concentrated at these high frequencies. In or-
der to make the load voltage insensitive to these noise frequency
components, this sensitivity transfer function must have a at
gain response of 0 dB in the low-frequency region while it must
roll off in the high-frequency region for better noise attenuation.
Combining (6) and (7) gives the load voltage dependence on the
two important sensitivity transfer functions as
v
0
(z
1
) = S
yp
(z
1
)

S
SLS
(z
1
)

+ S
yb
(z
1
)

n(z
1
)

(9)
where S
SLS
(z
1
)=[G
vg
(z
1
) v
g
(z
1
)+Z
0
(z
1
)

i
0
(z
1
)].
This equation plays a key role in the design of the controller
as it ensures the following: 1) CLC stability; 2) step source
and load disturbance rejection; and 3) noise suppression. In
order to make the load voltage insensitive to disturbances
and noise,

S
SLS
(z
1
) and n(z
1
) and the coefcient transfer
functions S
yp
(z
1
) and S
yb
(z
1
) need to be shaped properly
by assigning suitable PZ locations to the desired CHP.
In a properly designed CLC system, to ensure load voltage
regulation against the step load and source disturbances, the
duty ratio control signal has to undergo variations. To absorb
this effect, the controller must be designed properly such that
it reacts quickly enough to disturbances and a control signal
of suitable magnitude is generated, which must be within the
allowable range. In order to understand this phenomenon, the
following mathematical analysis is performed. In the SFG
shown in Fig. 3, there exists only one loop, and its loop
transmittance is L
T
= G
c
(z
1
)G
vd
(z
1
). The forward path
between disturbance signal ( p) and control duty ratio (

d) is
( p x
2
v
0
x
3
x
1


d), and its transmittance is p
T
=
G
c
(z
1
). There are no nontouching loops in the forward path
p
T
, and hence,
T
= 1; = (1 L
T
). Using Masons gain
formula(p
T

T
/), the CLC control signal dependence on the
disturbance is

d(z
1
) =

S
up
(z
1
)

p(z
1
)

(10)
where the control input sensitivity function S
up
(z
1
) =
G
c
(z
1
)/[1 + T
L
(z
1
)]. Equations (9) and (10) completely
Fig. 4. NP indicating modulus, gain, and phase margins.
dene the CLC dynamical behavior and its duty ratio signal
variation against disturbances. There are three important sen-
sitivity transfer functions S
yp
(z
1
), S
yb
(z
1
), and S
up
(z
1
),
and here, the controller G
cr
(z
1
) must be designed such that
all the STFs are within the template boundaries dened by the
robust stability performance parameters. The signicance of
these STFs is explained in the following section.
C. Digital Controller Robustness Verication
The CLC system will be robust if its stability is guaranteed
for a given set of converter parameter uncertainties. Theoreti-
cally, the robustness of the CLC is related to the minimal dis-
tance on the Nyquist plot (NP) between the nominal operating
condition and the critical point (1 + j0), as shown in Fig. 4,
as well as to the frequency characteristics of the modulus of
the sensitivity functions. In view of the parameter uncertainties,
the conventional frequency domain GM and PM specications
are inadequate measures to quantify the robustness of the CLC
system. For complete CLC system stability and robustness
quantication [30], the following four important parameters
need to be evaluated.
1) GM: The GM indicates the additional gain that would
take the closed loop to the critical stability condition. It is
equal to the inverse of the T
L
(z
1
) gain for the frequency
corresponding to a phase shift = 180

. This must be
at least 6 dB.
2) PM: The PM quanties the pure phase delay that should
be added to achieve the critical condition, and its range
for a stable system is 30
0
70
0
.
3) Modulus margin (M): This quantity gives a measure of
the robustness, and it is dened as the distance between
the stability point (1 + j0) and T
L
(z
1
). In mathemati-
cal terms, it is M = |1 + T
L
(z
1
)|
min
. For a stable and
robust CLC, it must be greater than -6 dB.
4) Delay margin (): The delay margin represents the
delay that can occur in the open-loop system before the
CLC system becomes unstable. This gives an alternative
way of expressing the PM, and if the NP intersects the
unit circle at several frequencies (
i
), then it is given by
= min
i
(
i
/
i
). A stable CLC system must have
> T
s
.
2888 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
From a robust control point of view, the performance objec-
tives of a feedback system can usually be specied in terms
of the requirements on the sensitivity functions S
yp
(z
1
),
S
yb
(z
1
), and S
up
(z
1
). Hence, the controller must be de-
signed by shaping the frequency-response characteristics of
these three sensitivity functions to achieve the following design
requirements: 1) load voltage regulation to set-point reference;
2) rejection of noise, step source, and load disturbances; and
3) stability and robust performance against converter parameter
uncertainty. To achieve these design objectives [34], the follow-
ing performance specication bounds must be ensured.
(a) Reference or set point tracking
|e|
|r|
=

S
yp
(z
1
)

<
r
, [0,
r
]. (11)
(b) Disturbance rejection
|y|
|p|
=

S
yp
(z
1
)

<
p
, [0,
p
]. (12)
(c) Stability robustness

S
yr
(z
1
)

< 1/

m
(z
1
)

. (13)
(d) Measurement noise to control signal noise rejection

S
up
(z
1
)

<
n
, [
n
,
p
]. (14)
The physical signicance of the bound
r
, over the frequency
range [0,
r
], on S
yp
is to maintain a constant load voltage even
under source and load uctuations. Larger values for
r
and
p
indicate poor performance as well as poor robustness. In the
frequency domain, the maximum amplitude of the frequency
response of the transfer function is obtained by computing the
norm of H

. Thus, the norm of H

, represented as

,
gives an important measure of gain, often used in controller de-
sign for measuring the peaks of the sensitivity functions. Hence,

r
= S
yp
(z
1
)

represents the maximum magnitude of the

output sensitivity function, for all possible parameter variations,
in the frequency range [0,
r
]. Furthermore, the modulus of
the inverse of the output sensitivity function gives, at each fre-
quency, the distance on the T
L
(z
1
) NP relative to the critical
point (1 + j0). To maintain the CLC stability, the loop gain
transfer function T
L
(z
1
) must be far away from the (1 + j0)
point. Furthermore, the tangential distance from (1 + j0) to
T
L
(z
1
), |1 + T
L
(z
1
)|, gives the modulus margin. Thus, for
robust stability, M (1/
r
). Therefore, the modulus margin
frequency template is the upper bound on the output sensitivity
function S
yp
. The noise-output sensitivity function S
yb
allows
the denition of a frequency template to ensure that the delay
margin constraint is fullled. For a delay margin of k sampling
periods [24], the robust stability condition is

S
yb
(z
1
)

< 1/

m
(z
1
)

(15)
where
m
(z
1
) = (z
k
1). From (5a) and (5c), it is easy to
establish the identity S
yp
(z
1
) S
yb
(z
1
) = 1, and therefore,
the range on S
yp
is obtained as

S
yb
(z
1
)

<

S
yp
(z
1
)

<

1 +

S
yb
(z
1
)

. (16)
Fig. 5. Templates for sensitivity functions. (a) Output sensitivity templates.
(b) Input sensitivity templates.
The aforementioned relationship shows the interdependence
of the sensitivity functions S
yp
(z
1
) and S
yb
(z
1
). In view of
this, formulating a bound on S
yp
(z
1
) automatically sets the
bound on S
yb
(z
1
).
The input sensitivity function gives information on the duty
ratio control signal, in the frequency domain, against distur-
bances. Since uncertainties in the converter parameters are
unavoidable, in such cases, the controller may generate ex-
cessively high duty ratio control signal against disturbances.
In order to ensure the robust stability of the CLC system, the
S
up
must be shaped, and an upper bound (
n
) must be set at
high frequencies. In a tradeoff design, the S
up
must be shaped
properly such that its magnitude is low in the frequency region
where the converter gain is very low [24]. From the aforemen-
tioned analysis, it can be noted that the sensitivity functions
describe the robust stability of the CLC system with respect to
model/parameter uncertainty [31]. Bounds on the magnitude of
the frequency-dependent model uncertainties convert to upper
constraints on the sensitivity functions. These upper bound
constraints, together with the modulus and delay margins, result
in the desired templates for the sensitivity functions, and their
typical sample templates are shown in Fig. 5.
The step-by-step RPIDC design procedure is discussed in the
following list.
Step 1: For the nominal operating conditions, formulate
the control-to-output z-transfer function of the HSBC,
G
vd
(z
1
). Dene the bounds on the sensitivity functions
depending on the nominal performance and robust stability
requirements.
Step 2: Choose the desired pole locations of the CLC system,
which involves the identication of the dominant and
auxiliary poles. The dominant pole locations are based
on the nominal performance requirements of the CLC
while the auxiliary pole locations depend on the controller
robustness requirement.
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2889
Step 3: Choose the PZ conguration of the controller, G
cr
(z
1
).
Just like the CLC, the poles are divided into dominant
and auxiliary poles, and here, the controller numerator
(R(z
1
)) and denominator polynomials (S(z
1
)) are also
expressed in the factored form indicating the xed and
exible parts. Choose the xed part of these polynomials
in order to meet the predened performance requirements.
In voltage regulation problems, it is necessary to provide
an integral action by choosing the denominator polynomial
xed part S
f
(z
1
) = (1 z
1
) so that the controller ef-
fectively eliminates the steady-state error. In the same way,
placing a pair of complex zeros in R(z
1
) or in S(z
1
)
decreases the magnitude of the modulus of the sensitivity
functions around the frequencies of these zeros.
Step 4: Solve (4), and then, formulate the controller polynomi-
als R(z
1
) and S(z
1
).
Step 5: Use the previously computed controller, and then,
generate the sensitivity functions, dened by (5), for the
expected parameter variation. Check that all the sensitivity
functions are within the prespecied boundaries. If any of
these extend beyond the boundaries, then the following
modications are helpful in bringing the sensitivity transfer
functions within the dened templates. If the maximum of
S
yp
is located in the frequency range next to the attenuation
band, then using a different damping factor, between 0.3
and 0.8, to the dominant poles brings the magnitude of S
yp
below the admissible value. If the maximum of the output
sensitivity function is located in the high-frequency range,
then shift the auxiliary poles toward the high-frequency
regions so that the S
yp
maximum shifts toward the lower-
frequency region. A similar exercise needs to be adopted
even for reshaping the S
up
sensitivity function.
Step 6: Repeat Steps 25 until the designed controller
G
cr
(z
1
) satises the stability and robust performance
specications.
Any controller which is stable and maintains load voltage
regulation may not necessarily satisfy all the robust perfor-
mance specications. However, the controllers which have been
designed based on the previously dened step-by-step design
procedure, involving the shaping of sensitivity functions which
are formulated according to the robust control theory, are
certain to meet all the specications.
IV. RESULTS AND DISCUSSIONS
In order to conrm the robust control concepts, developed
earlier and discussed in the preceding sections, simulation and
experimental studies have been carried out on a prototype soft-
switching boost dcdc converter. A 60-W 50-kHz 2442-V
HSBC is considered here to demonstrate the design concept.
Using a steady-state analysis, as discussed in Section II, the
converter parameters have been designed, and the correspond-
ing component values are listed in Table I. Discrete-time
models have been formulated, based on the analysis given
in Section II, and then used in the RPIDC design. For the
parameters listed in Table I, the control-to-output transfer func-
tion is obtained fromthe systemidentication methodology and
Fig. 6. Comparison of control-to-output transfer function accuracy obtained
from three different methods.
GSSA, respectively, [35], [36], as explained in Section II, as
follows:
1) System identication:
G
vd
(z
1
) =
v
o
(z
1
)

d(z
1
)
=
b
1
z
1
+ b
2
z
2
[1 + a
1
z
1
+ a
2
z
2
]
(17a)
2) GSSA:
G
vd
(z
1
) =
v
o
(z
1
)

d(z
1
)
=
b

1
z
1
+ b

2
z
2
[1 + a

1
z
1
+ a

2
z
2
]
(17b)
where b
1
=0.00682, b
2
=0.00657, a
1
=1.885, a
2
=0.8904,
b

1
=0.01946, b

2
=0.0301, a

1
=1.941, and a

2
=0.9482.
In order to compare the accuracy of this transfer function,
the frequency response of the control-to-output small-signal
transfer function is also generated using the following: 1) the
GSSA method and 2) the PSIM power electronic simulator.
These frequency response plots are shown in Fig. 6. From this,
it is clear that the transfer function obtained from system iden-
tication is closely matching with the frequency response ob-
tained from the PSIM simulator while the GSSA-based model
exhibits signicant deviation in the high-frequency region. In
view of this deviation, any given digital controller will yield
different GM, PM, and crossover frequencies. Furthermore,
this deviation affects signicantly the loop-gain design, and
sometimes, the direct use of such digital controllers may lead to
an unstable closed-loop converter system on account of lower
stability margins.
2890 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
We proceed to design a robust controller directly in the
z-domain, in the MATLAB [41] environment, using the step-
by-step procedure given in Section III-C. For the given A(z
1
),
B(z
1
), R(z
1
), and S(z
1
), the characteristic equation
P(z
1
) results in a fourth-order polynomial. Now, we have to
choose the desired CLCpoles
1

4
of X
dchp
(z
1
). As already
pointed out in Section III-A, the desired CLC poles are divided
into dominant and auxiliary poles, which are spread within the
unit circle and are also responsible for achieving the desired
load voltage regulation performance. Here, rst, we choose the
dominant pole locations by specifying the damping ratio (0.6 <
< 1) and frequency (
n
) corresponding to the slowest pole
of the converter. The poles and zeros of the HSBC for nomi-
nal operating conditions are pole
1,2
= (0.9430 j0.0505) and
zero
1
= 1.4525, and the frequency of the slowest pole
1,2
is
n
= 3920 rad/s. The aim is to design a proper controller,
where the controller transfer function numerator and denomi-
nator polynomials are of equal degree, using a PPT to achieve
load voltage regulation as well as robust performance. In the
PPT, the system order gives the basis for the controller and
desired CHP order selection. For an nth order system [38], the
controller and CHP order are (n 1) and (2n 1), respec-
tively. Since the converter under consideration is of the second
order (n = 2), the controller and CHP order are one and three,
respectively. We rst assign the desired CHP poles to p
1,2
=
0.97 ( = 1 and
n
= 1520 rad/s) and p
3
= 0.94 ( = 1
and
n
= 3090 rad/s), formulate X
dchp
(z
1
), and then solve
(4) to obtain the controller polynomials R(z
1
) and S(z
1
),
and the resulting controller is
G
c1
(z
1
) =
0.16152(1 1.007z
1
)
(1 0.9931z
1
)
. (18)
As the low-frequency gain associated with this controller
is low, the achievable stability margins are also smaller in
magnitude. In view of these, the robustness range of this
controller is restricted. Furthermore, there is a possibility of
having a steady-state error in the load voltage due to the lack
of a pole at z = 1. To demonstrate this fact, as well as to see the
sensitivity function dependence, the three STFs are generated
for the variable load (R = 25 40 ) and source voltages
(V
g
= 20 28 V) as shown in Fig. 7. The output sensitiv-
ity function is touching the modulus margin limit. Although
the noise sensitivity (S
yb
) is within the templates meeting
the allowable limits, the input sensitivity (S
up
) variation at
high frequencies is very small. For this reason, the controller
may not generate a sufcient duty ratio in order to maintain
constant load voltage, and hence, its disturbance rejection ca-
pability is low. This controller is suitable only for nominal
operating conditions, and it is not robust against parameter
variations.
To eliminate the steady-state error problem, the CHP poles
are now reassigned, p
1,2
= 0.973 ( = 1 and
n
= 1370 rad/s)
and p
3
= 0.9405 ( = 1 and
n
= 3070 rad/s), such that the
resulting controller has a pole at z = 1 and the corresponding
controller transfer function is
G
c2
(z
1
) =
0.14757(1 1.022z
1
)
(1 z
1
)
. (19)
Fig. 7. Sensitivity functions with G
c1
(z) controller.
Since this controller has a pole located at z = 1, the CLCsys-
tem exhibits a zero steady-state error against the step changes.
The robustness of this controller has been veried for the given
parameter uncertainty, and the corresponding STFs are drawn
in Fig. 8. For the assumed parameter variation, the S
yb
and S
up
sensitivity functions meet the allowable limits, but the output
sensitivity function (S
yp
) exceeds the modulus margin limits.
This deviation clearly indicates that this controller is unable
to meet the modulus margin limits, and hence, the controller
robustness is also restricted. Other combinations of the poles
p
1
p
3
may not yield compensator congurations with a pole
located at z = 1, and the corresponding controllers are unable
to meet steady-state error limits. In view of this limitation, other
possible controllers, one zero-one pole conguration, are not
discussed here.
The aforementioned discussion suggests that the one zero-
one pole conguration is unable to fulll simultaneously the
dynamic and steady-state requirements of the HSBC. The
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2891
Fig. 8. STFs with G
c2
(z) controller.
inclusion of an additional PZ pair gives more exibility in
reshaping the loop gain characteristic as well as the sensitivity
functions, and thus, second-order controller congurations are
now considered. In order to meet the CLC system performance
specications, the controller needs to satisfy certain additional
constraints. A standard requirement for most controllers is that,
in the steady state, the nominal control loop should yield zero
control error due to step disturbances. For this to be achieved,
a necessary and sufcient condition is that the nominal loop
should be internally stable [40] and that the digital controller
should have at least one pole located at z = 1. Some of
these requirements can be satised by the polynomial pole
assignment approach by ensuring that extra poles or zeros
are introduced. By introducing one pole for the system un-
der consideration, the CHP order now becomes 2n = 4, and
the corresponding controller order is n = 2. Furthermore, one
pole is xed at z = 1 so that all the controllers of the two
pole-two zero congurations are free from steady-state error
limitations.
Fig. 9. STFs with G
c3
(z) controller.
With a fourth-order characteristic polynomial, we begin with
the following pole assignment p
1,2
= 0.973 ( = 1 and
n
=
1370 rad/s), p
3
= 0.7 ( = 1 and
n
= 0.8 krad/s), and p
4
=
0.8 ( = 1 and
n
= 11.2 krad/s) to X
dchp
(z
1
); then, its
solution, (4), results in the controller polynomials R(z
1
) and
S(z
1
), and the corresponding controller is
G
c3
(z
1
) =
2.542[1 1.966z
1
+ 0.9675z
2
]
[1 1.5734z
1
+ 0.5734z
2
]
. (20)
With this controller, the STFs are generated for the expected
parameter uncertainty, and the corresponding plots are shown
in Fig. 9. From these STFs, it is clear that the maximum
output sensitivity is |S
yp
(z
1
)| = 1, satisfying the constraint
|S
yp
(z
1
)|
max
< 2. However, the input sensitivity function S
up
has a larger magnitude at high frequencies, indicating that the
duty ratio control signal of the HSBCmay exceed its upper limit
2892 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
in the presence of disturbances of higher magnitudes. Hence,
there is a need to look into other possible pole locations to
reshape the S
up
in the high-frequency region while enforcing
the boundaries on the other two sensitivity functions such that
the resulting controller has robust control performance.
The main requirement of the CLC is that its transient re-
sponse be sufciently fast and sufciently damped. This re-
quirement necessitates a nite value of damping (0 < < 1)
which must be present in the CLC, and this can be achieved
by introducing dominant complex conjugate poles in the CHP.
Here, the real part of the complex conjugate pair controls the
speed of the response while the imaginary part determines
the overshoot. In the case of a four-pole CHP, the dominant
pole is the complex conjugate pair
1,2
=
1
j
2
, (
2
1
+

2
2
< 1), while the auxiliary faster poles should be located
at
3,4
=
1
, ( <
1
), where
2
and need to
be chosen depending on the required range of robustness and
the type of expected uncertainties in the converter system.
In the discrete-time domain, the dominant poles must be within
the circle of radius r (|r| < 1) whose center is at the origin.
The radius of this circle depends on the and
n
of the
dominant poles (|r| e

n
T
s
). Assume that
n
= 3920 rad/s,
which corresponds to the frequency of the slowest pole of
the converter pole
1,2
, and that the damping (0.6 < < 0.9)
results in (0.93 <
1
< 0.95) and (0.034 <
2
< 0.0627). For
= 0.7, the pole locations are
1,2
= (0.9466 j0.056) and

3,4
= (0.9466 ).
Considering the dominance of the poles, one can choose
> (4
1
/5), but the inherent properties of the HSBC as well
as the robustness requirements will not allow such a selection.
Furthermore, for a xed-point nominal operating condition,
one can easily generate different sets of CHP poles just by
choosing the appropriate value of . However, to ensure CLC
stability as well as to realize the desired robust performance,
must be chosen judiciously such that the CLC system
STFs are within predened templates. Respecting the STFs
ensures minimum stability margins for the CLC system even
under the worst case of the expected operating point. It is better
to start with = 0, and by progressively increasing it in
the forward direction, one can reach the desired location in a
smaller number of iterations. Starting with = 0 gives the
CHP poles as
1,2
= (0.9466 j0.056) and
3,4
= 0.9466,
and the corresponding controller is
G
c4
(z
1
) =
0.23877[1 1.881z
1
+ 0.8867z
2
]
[1 1.9017z
1
+ 0.9017z
2
]
(21)
which gives GM = 53 dB, PM = 66
0
, DM = 34 samples,
and MM = 1.234 at the nominal operating condition. Al-
though this controller is capable of regulating the load voltage
both at the nominal operating condition and under distur-
bances, its starting performance has an overdamped nature.
Furthermore, the output and noise sensitivity functions shown
in Fig. 10 are within the allowable limits, but the S
up
sensitivity
function is lowat high frequencies, indicating that the controller
may not generate a duty ratio signal of high enough magnitude
for load voltage regulation against high-frequency disturbances.
MATLAB simulations have been performed for several dif-
Fig. 10. STFs with G
c4
(z) controller.
ferent combinations of (
1
, ), and in each case, the CLC
performance has been tested for stability and robustness. The
following CHP poles
1,2
= (0.96 j
2
) and
3,4
= 0.9 re-
sult in a robust controller with the following characteristics:
1) respecting the sensitivity functions for the expected param-
eter variation; 2) resulting in an almost critically damped
starting response under nominal operating conditions; and
3) better disturbance, source, and load rejection. The corre-
sponding robust controller congurations, for three different
values of
2
(= 0.01, 0.05, 0.065), are
G
cr1
(z
1
) =
0.2357[1 1.942z
1
+ 0.974z
2
]
[1 1.8352z
1
+ 0.8352z
2
]
(22a)
G
cr2
(z
1
) =
0.4147[1 1.878z
1
+ 0.8858z
2
]
[1 1.8362z
1
+ 0.8362z
2
]
(22b)
G
cr3
(z
1
) =
0.4594[1 1.87z
1
+ 0.878z
2
]
[1 1.8364z
1
+ 0.8364z
2
]
. (22c)
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2893
Fig. 11. STFs with G
cr2
(z) controller.
By taking these controllers, various stability margins have
been obtained, and it is found that they are within allowable lim-
its. Furthermore, sensitivity functions indicative of robustness
have also been generated for load (R = 40 25 ) and source
voltage (V
g
= 20 28 V) variations as shown in Fig. 11 for
G
cr2
(z
1
). The aforementioned theoretical analysis provides
insight into robust controller design, and to validate this design
in reality, one must verify its practicability with regard to con-
verter dynamics and the required standard of control quality in
terms of the maximum allowable overshoot, accuracy, settling
time, etc. To this effect, a prototype HSBC CLS has been
built and tested under nominal controller conditions and for
robustness. The detailed discussions are given in the following
paragraphs.
To verify the digital controller design methodology and its
robustness, as discussed earlier, simulations have been per-
formed on the PSIM platform [42] and then veried with
a laboratory prototype converter system. To demonstrate the
robustness of the designed controller, variations in the supply
voltage and load were created. It is assumed that a constant
Fig. 12. Simulated starting response of the load voltage with different source
voltages (R = 30 ; CV
1
= 28 V; CV
2
= 24 V; CV
3
= 20 V).
Fig. 13. Simulated starting response of the load voltage with different source
voltages (R = 30 ; CV
1
= 28 V; CV
2
= 24 V; CV
3
= 20 V).
source voltage (CV ) has possible relative uctuations of 15%
about the nominal value (V
g
: 20 28 V); similarly, the rela-
tive load variation is about 20% of the nominal value (R :
25 40 ). The simulation results obtained with the robust
controller G
cr2
(z
1
), shown in Figs. 12 and 13, indicate the
following: 1) a start-up response that is critically damped and
exhibits a minimum rise time at the nominal operating condi-
tion; 2) a better load voltage regulation against disturbances
such as source voltage (V
g
: 20 28 V) and load variation
(R : 25 40 ), with a minimum settling time; and 3) over
or undershoots during the step source and load variations are
less than 12%.
To validate the theoretical analysis that has been devel-
oped and the simulation results, a laboratory prototype CLC
system has been built and tested for regulation and robust-
ness. The digital control algorithm has been implemented us-
ing a dsPIC30F6010 digital signal controller [43]. The de-
vices used in the prototype converter circuits are as follows:
switch IRF540, diode MUR860, driver circuit IR2110, and
optoisolator 6N137. The load voltage is sensed and is brought
within the range (05 V), which is passed on to the onboard
analog-to-digital converter of the dsPIC. The digital controllers
G
c1
(z
1
)G
c4
(z
1
) and G
cr1
(z
1
)G
cr3
(z
1
) were trans-
formed into discrete-time forms and then listed in Table II for
ready use in experimentation.
2894 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
TABLE II
DIGITAL CONTROL LAWS FOR DIFFERENT CHP POLES
First, the controller G
c1
(z
1
) load voltage regulation capa-
bility has been tested against the load change R : 25 40 ,
and the measured dynamic response is plotted in Fig. 14(a). It
is clear that this controller exhibits a steady-state error in the
load voltage due to the lack of a pole at z = 1. The controller
G
c2
(z
1
) load voltage regulation capability has been tested
against the load change R : 25 40 for different source
voltages (CV
1
= 28 V, CV
2
= 24 V, and CV
3
= 20 V) as
shown in Fig. 14(b). Although this controller is regulating
the load voltage and rejecting the load disturbances for CV
1
,
a considerable steady-state error in the load voltage can be
seen for other operating conditions, such as CV
2
and CV
3
.
Hence, this controller is not suitable for ensuring the predened
robustness range. A similar kind of dynamic response tests have
been conducted on the HSBC with the G
c3
(z
1
) and G
c4
(z
1
)
controllers, and the measured dynamic responses, plotted in
Fig. 14(c) and (d), reveal that they are not robust for the CV
3
case. Although the digital controllers G
cr1
(z
1
)G
cr3
(z
1
)
are robust as the STF variation, against parameter uncertainty,
is within the admissible limits as shown in Fig. 11, the cor-
responding dynamic response results plotted in Figs. 15 and
16 suggest that G
cr1
(z
1
) needs more time to respond while
G
cr3
(z
1
) is faster in response with oscillatory behavior. On the
other hand, G
cr2
(z
1
) exhibits tradeoff dynamic performance
and less response time, together with minimumoscillations, and
such a controller would be better from the robustness point of
view. The measured starting response of the load voltage with
the G
cr2
(z
1
) controller is obtained for three different voltages,
as shown in Fig. 17, and it is clear that the dynamic response is
almost critically damped for the nominal operating condition.
The robustness of the controller against parameter variation
is also veried. Although several parameters can be varied
either simultaneously or one parameter can be varied at a time
and, in each case, the robustness of the controller as well as its
regulation capability can be recorded, for illustration, here, the
controller robustness and regulation are measured against the
following: 1) gradual source voltage variation; 2) gradual load
variation; and 3) inductance L variation. For the inductance
variation, an E-Ecore is used, and its L-variation is created by
Fig. 14. Measured dynamic response of the load voltage with different
controllers (different source voltages: CV
1
= 28 V, CV
2
= 24 V, and CV
3
=
20 V). (a) With G
c1
(z
1
). (b) With G
c2
(z
1
). (c) With G
c3
(z
1
).
(d) With G
c4
(z
1
).
introducing an air gap. Initially, the circuit operates with an
air gap in the inductor L, and it is varied by bringing the E-E
cores together. Experimental results (inductor current and load
voltage) have been recorded for these variations and plotted
in Fig. 18. It can be noted that the controller G
cr2
(z
1
) is
yielding robust performance even for L-variation (L : 260
320 H). For a given load, the robustness of the controller
against supply voltage variation is also veried as shown in
Fig. 19. It can be seen that, for the parameter variation falling
inside the robustness range, the controller maintains a constant
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2895
Fig. 15. Measured dynamic response of the load voltage with different
robust controllers (different source voltages: CV
1
= 28 V, CV
2
= 24 V, and
CV
3
= 20 V).
Fig. 16. Measured dynamic response of the load voltage with different robust
controllers (R = 30 ).
load voltage while it deviates from tracking the reference for
variations exceeding the robustness range.
Although all the digital controllers G
c1
(z
1
)G
c4
(z
1
),
G
cr1
(z
1
), and G
cr3
(z
1
) regulate the load voltage, the robust
controller G
cr2
(z
1
) designed in this paper responds quickly
enough and reaches the reference load voltage in a shorter time.
The measured performance of the robust controller G
cr2
(z
1
)
for extreme cases is also shown in Figs. 1517, where the
dynamic response settling time and overshoot quantities are
within the specied limits. Furthermore, the robust controller
exhibits a smaller response time during start-up and a shorter
settling time against step source and load perturbations, indi-
Fig. 17. Measured starting response of the load voltage with different source
voltages (R = 30 ; CV
1
= 28 V; CV
2
= 24 V; CV
3
= 20 V).
Fig. 18. Measured robustness indicating the plots of load voltage and inductor
current against inductance variation (L : 260 320 H).
Fig. 19. Measured load voltage robustness with different load resistances
(V V
1
= 40 , V V
2
= 30 , and V V
3
= 20 ).
cating better disturbance rejection capability. The design of a
digital controller to ensure the required range of robustness
range, together with a smaller response time, may not be
2896 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
feasible. In order to accommodate inaccuracies due to modeling
errors, the robustness range must be limited, or the response
time must be moderate in order to allow wider parameter
variation.
The experimental measurements are in close agreement with
those obtained in the theoretical studies and simulations. Slight
discrepancies between the simulation and experimentally mea-
sured results are attributed to the following factors: 1) The
supply voltage step variations created in the laboratory envi-
ronment may not be exactly those created in the simulations;
2) the dc supply source may not be as stiff as assumed in the
simulations; 3) difculty in including actual nonidealities of the
experimental system in the simulation environment; 4) a slight
mismatch of the mathematical models may cause differences
between the simulation and experimental dynamic responses;
5) analytically obtained dynamic responses also partly gov-
erned by the type of simulation engine used, etc.
V. CONCLUSION
An RPIDC for an HSBC has been designed. Discrete-time
models were formulated through system identication tools and
then used in the design of the digital controller. A PPT, together
with SFS, has been applied to establish design guidelines for
digital controller design. By choosing the desired CHP poles,
controllers were designed, and then, to ensure a robust sta-
bility input, output and noise determining sensitivity function
variations, over a predetermined range of frequencies, have
been obtained. For a predened range of parameter uncertainty,
if all the sensitivity functions are within allowable templates,
then the corresponding controllers are classied as robust con-
trollers. The sensitivity-function-based robustness that has been
developed has been veried by simulation and experimental
measurement. These investigations reveal that CHP complex
conjugate pole damping has a substantial effect on the achiev-
able range of robustness, speed of response, and overshoot. Less
damping results in faster regulation at the expense of increased
overshoot and reduced robustness range, and vice versa. Hence,
a tradeoff between the damping and placement of complex
conjugate poles would be a better choice, and the damping
value depends on the range of the expected uncertainty in a
given CLC system and on the speed of the response required
by the application.
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Veerachary Mummadi was born in Survail, India,
in 1968. He received the B.Tech. degree from the
Jawaharlal Nehru Technological University (JNTU)
College of Engineering-Anantapur, Anantapur,
India, in 1992, the M.Tech. degree from the
Regional Engineering College, Warangal, India, in
1994, and the Dr. Eng. degree from the University
of the Ryukyus, Okinawa, Japan, in 2002.
From 1994 to 1999, he was an Assistant Pro-
fessor with the Department of Electrical Engineer-
ing, JNTU-Anantapur. From October 1999 to March
2002, he was a Research Scholar with the Department of Electrical and Elec-
tronics Engineering, University of the Ryukyus. Since July 2002, he has been
with the Department of Electrical Engineering, Indian Institute of Technology
Delhi, New Delhi, India, where he is currently an Associate Professor. His
research interests include power electronics and applications, the modeling and
simulation of large power electronic systems, the design of power supplies for
spacecraft systems, control theory application to power electronic systems, and
intelligent solutions for power supplies.
Dr. Mummadi is an Editorial Member of The Institution of Engineering
and Technology (IET) Proceedings on Power Electronics, IET, U.K., and
the Journal of Power Electronics. He served as one of the Guest Editors of
the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS for two special
sessions on Photovoltaic Power Processing Systems and Efcient and Re-
liable Photovoltaic Systems. He is currently an Associate Editor of the IEEE
TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS and the IEEE
TRANSACTIONS ON INDUSTRIAL ELECTRONICS. He was the recipient of the
IEEE Industrial Electronics Society Travel Grant Award for the year 2001, the
Best Paper Award at the International Conference on Electrical Engineering
2000 held in Kitakyushu, Japan, and the Best Researcher Award for the year
2002 from the President of the University of the Ryukyus. He is listed in the
Whos Who in Science and Engineering, 2003.