FET Biasing
FET Biasing
FET Biasing
CHAPTER 6
Introduction
For the JFET, the relationship between input and output
quantities is nonlinear due to the squared term in
Shockley’s equation.
Nonlinear functions results in curves as obtained for
transfer characteristic of a JFET.
Graphical approach will be used to examine the dc
analysis for FET because it is most popularly used rather
than mathematical approach
The input of BJT and FET controlling variables are the
current and the voltage levels respectively
Introduction
JFETs differ from BJTs:
• Depletion-Type MOSFET
– Self-Bias
– Voltage-Divider Bias
• Enhancement-Type MOSFET
– Feedback Configuration
– Voltage-Divider Bias
General Relationships
For all FETs:
IG ≈ 0A
ID = IS
I D = k (VGS −VT ) 2
Fixed-Bias Configuration
The configuration includes the ac levels Vi and Vo and
the coupling capacitors.
The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.
Fixed-Bias Configuration
For the DC analysis,
Capacitors are open circuits
I G ≅ 0 A and V
RG = I G RG = (0 A) RG = 0V
The zero-volt drop across RG permits replacing RG by a short-circuit
Fixed-Bias Configuration
Investigating the input loop
IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration due to VGG is a fixed
power supply so VGS is fixed VGS 2
ID = IDSS(1− )
The resulting current, VP
Investigating the graphical approach.
Using below tables, we
can draw the graph
VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
The fixed level of VGS has been superimposed as a
VGS = −VGG
vertical line at
At any point on the vertical line, the level of VG is -VGG---
the level of ID must simply be determined on this vertical
line.
The point where the two curves intersect is the common
solution to the configuration – commonly referrers to as
the quiescent or operating point.
The quiescent level of ID is determine by drawing a
horizontal line from the Q-point to the vertical ID axis.
Output loop
V DS = VDD − I D R D
VS = 0V
VDS = VD − VS
VD = V DS + VS VS = 0
VD = V DS
VGS = VG − VS
VG = VGS + VS VS = 0
VG = VGS
Example
Determine VGSQ, IDQ, VDS, VD, VG, VS
Exercise
Determine IDQ, VGSQ, VDS, VD, VG and VS
Self Bias Configuration
The self-bias configuration eliminates the need for two
dc supplies.
The controlling VGS is now determined by the voltage
across the resistor RS
Forthe indicated input loop:
VGS = − I D RS
Mathematical approach:
2
VGS
ID = I DSS
1 − V
P
2
I D RS
ID = I DSS
1 − V
P
rearrange and solve.
Graphical approach
Draw the device transfer characteristic
Draw the network load line
Use VGS = − I D RS to draw straight line.
First point, I D = 0, VGS = 0
Second point, any point from ID = 0 to ID = IDSS. Choose
I DSS
ID = then
2
I R
VGS = − DSS S
2
V DS =V DD − I D ( RS + R D )
VS = I D RS
V D =V DS +VS =V DD −V RD
Example
Determine VGSQ, IDQ,VDS,VS,VG and VD.
Example
Determine VGSQ, IDQ, VD,VG,VS and VDS.
Voltage-Divider Bias
The arrangement is the same as BJT but the DC analysis is
different
In BJT, IB provide link to input and output circuit, in FET VGS does
the same
Voltage-Divider Bias
The source VDD was separated into two equivalent sources to permit
a further separation of the input and output regions of the network.
IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the series
equivalent circuit appearing to the left of the figure can be used to
find the level of VG.
Voltage-Divider Bias
VG can be found using the voltage divider rule :
R2VDD
VG =
R1 +R2
Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS:
VG −VGS −V RS = 0
VGS = VG − I D RS
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.
Once the quiescent values of IDQ and VGSQ are determined, the
remaining network analysis can be found.
V DD
I R1 = I R 2 =
R1 + R2
VS = I D RS
Effect of increasing values of RS
Example
Determine IDQ, VGSQ, VD, VS, VDS and VDG.
Example
Determine IDQ, VGSQ, VDS, VD and VS
Depletion-Type MOSFETs
Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is
that the depletion-Type MOSFETs can operate with positive values of VGS and with
ID values that exceed IDSS.
Depletion-Type MOSFETs
The DC Analysis
Same as the FET calculations
Plotting the transfer characteristics of the device
Plotting the at a point that VGS exceeds the 0V or more positive values
Plotting point when VGS=0V and ID=0A
The intersection between Shockley characteristics and linear
characteristics defined the Q-point of the MOSFET
The problem is that how long does the transfer characteristics have to
be draw?
We have to analyze the input loop parameter relationship.
As RS become smaller, the linear characteristics will be in narrow slope
therefore needs to consider the extend of transfer characteristics for
example of voltage divider MOSFET,
VG −VGS −V RS = 0
VGS = VG − I D RS
The bigger values of VP the more positive values we should draw for the
transfer characteristics
Analyzing the MOSFET circuit for DC
analysis
How to analyze dc
analysis for the shown
network?
Itis a …. Type network
Find VG or VGS
and
I D ( on )
k=
(VGS ( on ) − VGS (Th ) ) 2
Feedback Biasing Arrangement
Again plot the line and the transfer curve to find the Q-point.
Using the following equations: R2VDD
VG =
R1 + R2
Input loop : VGS = VG − I D RS
Output loop : V DS = V DD − I D ( RS + R D )
Voltage-Divider Bias Q-Point
• Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID = VG/RS
and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS(on), ID(on); all given in
the specification sheet.
4. Where the line and the transfer curve intersect is the Q-Point.
5. Using the value of ID at the Q-point, solve for the other variables in the
bias circuit.
Example
Determine IDQand VGSQ and VDS for
network below
=-
= -
= -
= - ( + )
=
+
= -
= - ( + )
= -
= + - ( + )
=
=
=-
=
=
= -
=-
= -
=
+
= -
= - ( + )
=
= -
=
+
= -
Troubleshooting
N-channel VGSQ will be 0V or negative if properly checked
Level of VDS is ranging from 25%~75% of VDD. If 0V
indicated, there’s problem
Check with the calculation between each terminal and
ground. There must be a reading, RG will be excluded
P-Channel FETs
For p-channel FETs the same calculations and graphs are used, except
that the voltage polarities and current directions are the opposite. The
graphs will be mirrors of the n-channel graphs.
Practical Applications
• VoltageControlled Resistor
• JFET Voltmeter
• Timer Network
• Fiber Optic Circuitry
• MOSFET Relay Driver