Week 1

wed intro to the embedded systems,small,medium and large scale es from Raj Kamal ch 1.11,real time os (RTOS) components of the 02/01 (zmp) embedded system,processors : von-neumam and hardward architecture. RISC vs CISC,SIMD MIMD and superscalar processor, pipeline processing . intro to 8051,detailed architecture,pin diagram.Ayala ch 2 (posted) transistor revolution, development of digital logic families, semiconductor physics and equations review. winspice design of R-C circuit. overview ch 3 : Data Communication issues from stallings 8th ed **, ch6 6.1,6.2,6.3,6.5 and overview of 6.4(to be continued maybe!!). **(https://docs.google.com/open? id=0B8J6rn43NndeeUFCdVRDdThrSFk) only overview in class and lab B1 : manual will be posted as soon as received. The book to be followed is Fiber optic communication by VM sir. VLSI fabrication video already posted.

ES
fri wed fri wed

thurs 03/01 (zmp) 04/01 RP 02/01 (ADD) 04/01 B1 02/01 (Div) 04/01 (div)

DIC

DCN

fri

FOC

NAN

Week 2 ES
wed 09/01 (zmp) RISC architecture time period and efficiency,typical pipeline,memories and timers-counters,RTC,watch dog timer. on board and external communication, I/O,software development (assembly and C) Port architecture(0,1,2,3), addressing modes,arithmetic and logical instruction instructions. Basic add multiply instructions in keil uVision create and save new project. Amtel 8051 AT89C51

thurs 10/01 (zmp) fri lab 11/01 RP

 new file xy.a51,add to source group by right clicking on source group. After writing programm,build and rebuild debug (F11 for line by line) and use disassembly window for more detailed (mnemonics with hex code) view. Target/options/output/hex file. No halt so need sjmp to loop the control at the end line. mon 07/01 (AJ) 10/01 (AJ) Lab B1 RTL- fanout,propogation delay,nor,wired anding, convention: Rc=640,Rb=450,Vcc=3v,Vbe(sat)=0.75,Vce(sat)=0.2 Loading capacitance,V1=0.8,Ic=4.4m,Ib=0.1m,B=50 Fanout for n o/p gates with Vy=[0.65 0.64 ....0.64]n Io=100+(n-1)320=3400u,Io=(3-0.8)/640=3.4m,so n=11. Plot the i/p and o/p char for short channel and long channel NMOS and PMOS and derive rd,gm,Ion,Ioff,subthreshold swing for all. Protocol architecture-different layers,multilayer communication, TCP/IP layers, Concept of framing, physical and ogical address, flag and esc characters in a frame for asynchronous distinction. Esc for esc can be avoided by bit stuffing the dummy esc character. Forouzen 4th ed 11.1 Framing (**https://docs.google.com/file/d/0B8J6rn43NndeVVVFZVdqNy1t S1k/edit) Ipconfig /all,/renew,/release ping with its attributes tracert www.facebook.com ping -j (x ip) ( intermidiate ip) (y ip) 07/01 (PNP) Advantages : 1] carry large amount of data 2] higher data rate (10Gb/s) 3] no electric current or EMI 4] good security 5] no corrosion in water Disadvantage : higher initial infrastructural cost and problem of splicing. Elements of tx link: optical source/optical modulator<-- i/p/fiber medium/detector/demod/o/p signal.

DIC thur
fri

wed

09/01 (AR) Div

DCN fri

11/01 (div)

lab

FOC mon

tues fri lab

08/01 (VM) 11/01 (VM)

General requirements of the light source,types of sources and spectral intensity, Absorption ,spontaneous and stimulated emission of ratiation,Einstein relations,population inversion,fabri-parot cavity resonator,major loss. Characteristics of LED. - MOS capacitance, Rh,Q', - Scaling effects: Sio2 becomes very thin, which causes gate tunneling. For very small channel, the gate control is lost. Optical methods are used for parameter checking as we can no more use probe to do physical measurements. For the same device, effective geometry changes at nano scale, for eg , MOS channel becomes trapezoidal in place of rectangular. Multilevel metalisation is done to reduce R and thus it reduces RC delay. Poisson's eq, Fermi-dirac distribution, types of the semiconductors.

wed

(09/01)

NAN
thurs (10/01)

Week 3 ES
wed RTS- real time system, hard and soft RTS, value vs tardiness,examples,performance parameters of SRTS, RTOS 16/01 (zmp) definition ,app s/w to hardware hiearchy. ( All from slides)

thurs 17/01 (zmp) ( All from slides) what is process or task,status and state siagram for process, jobs of RTOS: scheduling the process memory allocation IO management this memory is called kernal area,which is not interrupted by the user application memory space. POSIX standards for the syntax of the API's (system functions) concept of threads,individual memory area for each process and private status for each thread fri 18/01 RP Ayala ch2 Timers and counters 43-47 of ebook

timer 0 and 1 are 16 bit reg each of 2 one byte register pairs TL and TH. TCON is 8 bit addressable in which overflow and run status of both T0 and T1 is stored.Lowe nibble is used as interrupt. TMOD is also bit addressable 8 bit reg to select S/W or H/W,C/T',and the modes of timer 0 and 1.Bits of TMOD,

wed

16/01 (ADD) Kang 3.1 and 3.2 MOS structure and external bias. 17/01 (AJ) Lab B1 Rise time with load Tr=(640N+450)C, RTL buffer,which can handle higher fanout Model of RTL nor,truth table,VTC,noise margin,transient analysis. Forouzen (**https://docs.google.com/file/d/0B8J6rn43NndeVVVFZVdqNy1t S1k/edit) 11.2 flow and error control,11.3 protocols,11.4 noiseless channel,11.5 noisy channel stop and wait ARQ ch 11 forouzen Sliding window concept.Why size of the frame is 2^m -1 D-10 bit sequence T= 32D+FCS 15 bit sequence P=divider 10111 write a C program for CRC

DIC thur
fri

wed

16/01 Div

fri

17/01 (div)

DCN

lab

int d1=0,p=39,r,t,i=0; char d[10],t1[15]="000000000000000"; scan d string convert to decimal(d1) r=d1%p,t=d1*32+r convert t to bitstring t1 16/01 (PNP) applications of fiber optics,mounting the cable (keiser),basic link, mux, spectrum 50-400 UV 400-700 visible 800-1600 near IR 1600-100000 far IR In FOC carrier is light and the intensity/power is modulated, bands, three optical windows for silica fiber,SONET STS SDH (electrical equivalent standards).

FOC wed

fri

18/01 (VM)

Relative amplitude Vs f for laser,longitudinal modes and transverse modes,threshold condition for laser oscillation Photonic cad esg,dfb/mz/smf1/rx(pin)/eye openning,BER link implementation read: 3.2.1 dfb rate 4.1.1 Rx pin 4.1.2 Rx pin APD 5.2.1 SMF,MZ 7.1 mux 9.1.1 11.1,2,3,4,9,11

lab

wed

(16/01)

Schrodinger eq for electron in 1D finite L lattice,1D well model Solution of 1D well model and KP model colinge ch 1

NAN

thurs (17/01)