BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

Course Title ADVANCED VLSI DESIGN

Course No MEL ZG623
Instructor – In- Charge PREMANANDA B. S.

# Course Objectives

CO1 Apply the concept of deep submicron device engineering

CO2 Analyse the power/timing issues design , I/O circuit, clock signal generation/
distribution for synchronous and asynchronous VLSI systems

CO3 Students will be able to learn crucial real world design issues choose, such as signal
integrity, power dissipation, interconnect, timing & synchronization

CO4 familiarize the with the process of implementing a digital system as a full-custom
integrated circuit

CO5 Comprehend high speed computer arithmetic algorithms

# Student: Learning Outcomes

LO1 Upon completion of this course students will be able to develop sequential logic circuits .

LO2 Students will be able to identify metastable states and hazards, and should be able to
provide solution to them.

LO3 Students will be able to explore the basic components widely used in data paths, These
include basic combinational and sequential components application for arithmetic
operations, including addition, subtraction, multiplication

LO4 Students will be able to design the components of digital PLL and develop its
applications, . Application of All digital PLL(ADPLL) &DLL
 LO5 Students will learn broad variety of types of semiconductor memories,. The students will
be able to design SRAM

LO6 Students will be able to analyze the timing issues of systems based
on Flip-Flops, latches, and pulsed latches

LO7 Students will be able to develop modeling of wires for delay estimation in deep
submicron designs.

Text Book(s)
T1 -A design
Second Edition, Prentice Hall Electronics and VLSI Series

Reference Book(s) & other resources

R1

R2 John P. Uyemura , Introduction to VLSI Circuits and syatems Wiley

R3 Ming-Bo Lin Introduction to VLSI systems A logic circuit and system prespective
, CRC press. Taylor & Francis Group
R4 John P. Uyemura, CMOS LOGIC CIRCUIT DESIGN Kluwer Academic Publishers

R5 William J Dally, John W Poulton, " Digital Systems Engineering"; Cambridge

University Press

R6 Eric Bogatin, " Signal integrity Simplified", Prentice Hall Modern Semiconductor
Design Series
R7 IEEE Papers
 Detailed Structure
Type duration Title Description References
CS1 2hrs Introduction & Scaling Theory, deep submicron (DSM), R3 : chapter 1
Lab Design Issues of VLSI Systems, TSPICE Manual
Demonstration. Acquaintance with TSPICE
CS2 2hrs Sequential logic Static latches, Transmission Gate, D Flip T1: Chapter 7
circuit Flop, Edge triggered D Flip-Flop, Flip-
Flop Timing , SR flip flops, Metastable
States and Hazards
CS3 2hrs Dynamic latches Dynamic logic circuits, TG based T1: Chapter 7
2
& Registers Dynamic latch,C MOS Latch,
TSPCR,,Dynamic flipflops
CS4 2hrs Timing Issues in Issues in flip flop,& latch, max delay& T1: Chapter 10
Clocked Systems min delay constraint, clock skew & jitter,
clock distribution techniques
CS5 2hrs Clock Clock Generation Circuits, Clocks and T1:chapter10
Generation and Synchronization, clocking schemes, R4: chapter 7
Distribution synchronization using PLL R1,R2
Networks improvement of clk skew,Delay Locked
loops(DLL)
CS6 2hrs Asynchronous Asynchronous pipelining, self timed T1:Chapter 10
system design circuits applications, Handshaking R2: Chapter 10
Muller c-element,Adder circuit, Self
timed circuit applications
CS7 2hrs Interfacing Schmitt circuit, level shifting R3: chapter 15 &
circuits circuits.output driver buffers, Design for R2 chapter 11
SSN reductions,Terminators
CS8 2hrs Interfacing Electrostatic Discharge Protection R3: chapter 15 &
circuits Networks(ESD), ESD models, Diode & R2 chapter 11
MOS ESD circuit,
Mid semester Exam: Closed book
 CS9 2hrs Wire design Electrical wire models, Transmission lines, T1:Chapter 10
principles in R3 chapter 13
nanometer R6
region
CS10 2hrs Wire design Parasitic E_ffects of T1:Chapter 10
principles in Interconnect,crosstslk,RLC effect, Self-Timed R3 chapter 13
nanometer Regenerators (STRs) R6
region
CS11 2hrs Datapath Priority encoder, domino logic MUX, R3: chapter10
subsystem magnitude comparators
design
CS12 2hrs High speed The full adder,Ripple carry adder, , High speed T1: chapter 11
computer adders,carry skip circuits, Manchester carry R3: chapter10
arithmetic chains,Extension to wide adders, Parallel-Prefix R2: chapter 12
algorithms Adders
and design,
CS13 2hrs Computer Multipliers, Array multipliers, carry save T1: chapter 11
arithmetic multipliers,Booth multiplier, Baugh-Wooley R3: chapter10
Multipliers barrel shifter, logical/arithmetic-left R2: chapter 12
logarithmic barrel shifter
CS14 2hrs Logical Power & speed tradeoffs in data path structures T1: chapter11
Efforts
CS15 2hrs Deep Scaling Theory constant-_FIeld and constant- R3: chapter2
submicron voltage scaling, channel-length modulation,
device velocity saturation, and hot carriers, body
engineering effect, short-channel
effect (SCE),
CS16 2hrs Deep and drain-induced barrier lowering (DIBL) R3: chapter2
submicron Leakage Currents, Gate Leakage Current,
device Short-Channel I-V Characteristics, Thin-Oxide
engineering Breakdown
Comprehensive exam

Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1 Quiz-I Online - 5% September 10-20, 2020
Quiz-II 5% October 20-30, 2020
Assignment 10% November 10-20, 2020
EC-2 Mid-Semester Test Closed 2 hours 30% Saturday, 10/10/2020 (AN)
Book 2 PM – 4 PM
EC-3 Comprehensive Exam Open 3 hours 50% Saturday, 28/11/2020 (AN)
Book 2 PM – 5 PM
 List of Experiments:
1. For the two series connected inverter find the rise time and fall time and the total
delay. Develop a schematic diagram of the circuit and show the spice simulation result

3. Implement and simulate the operation of a 2to 1 Mux using transmission gate. Find the delay
and the observe effect of capacitive load at the output
4. Compare the performance of a basic Latch circuit developed with cross coupled inverter
with that of a Latch circuit having a TG in the feedback path of a Latch circuit
developed with cross coupled inverter .
5. Design and simulate an edge triggered flip-flop using level sensitive latches & to examine
the Hold time and setup time
6. Identify metastabilty in the given circuit and show a remedy to avoid stability.
7. Design and simulate the operation of a PE gate that will implement the logical function

8. Simulate the operation of the clocked CMOS latch

9. Design and simulate the operation of a Half Adder circuit using TG gate
10. Design a current-starved VCO with fcentre = 100 MHz in the short-channel process .Simulate
the design using SPICE.
11. Verify, using simulations, that a locked PLL using an XOR PD will exhibit, after RC
filtering, an average value of VDD/2. Show, using simulations and hand calculations, the
filter s average output if the XOR PD sees a phase difference in its inputs of /4.
12. Simulate the operation of the SRAM cell seen in Fig. . Use the 50 nm process with NMOS
of 10/1 and PMOS of 20/1. Is it wise for the access MOSFETs to be the same size as the
latch MOSFETs? Why or why not? Use simulations to verify your answers.
13. Design a nominal delay line of 1 ns (when VINDEL = 500 mV) using the current starved
delay element shown in Fig. Determine the delay's sensitivity to variations in VDD.