LIST OF EXPERIMENTS

S.no

Name of the experiment

Page no

1.

DC POWER SUPPLY DESIGN USING BUCK BOOST CONVERTERS

2.

DC POWER SUPPLY DESIGN USING FLY BACK CONVERTER

3.

DESIGN OF AC/DC VOLTAGE REGULATOR USING SCR

4. 5. 6. 7. 8. 9. 10. 11.

DESIGN OF PROCESS CONTROL TIMER PCB LAYOUT DESIGN USING CAD STUDY OF AMPLITUDE MODULATION AND DEMODULATION STUDY OF FREQUENCY MODULATION DESIGN OF WIRELESS DATE MODEM FREQUENCY MODULATOR DESIGN OF FSK MODULATOR USING 555 TIMER DESIGN OF INSTRUMENTATION AMPLIFIER

GENERAL PROCEDURE FOR ORCAD 9.2 TOOL 1. Launch Capture. (Start/programs/orcad10/capture CIS) 2. From the File menu, choose New > Project. 3. In the New Project dialog box, specify the project name. 4. To specify the project type, select Analog or Mixed A/D. 5. Specify the location where you want the project files to be created and click OK. 6. In the Create PSpice Project dialog box, select the Create a blank project option button. 7. Click OK to create the project with the above specifications. 8. From the Place menu in Capture, select Part. 9. In the Place Part dialog box, first select the library from which the part is to be added and then instantiate the part on the schematic page. 10. From the Part List, select the component and click OK. 11. Place the components on the schematic page as shown in the circuit and Right-click and select End Mode. 12. From the Place menu, choose Wire. The pointer changes to a crosshair. 13. Add wires to the design until all parts are connected as shown in the circuit. 14. To stop wiring, right-click and select End Wire. The pointer changes to the default arrow. 15. From the PSpice menu, choose New Simulation Profile or Edit Simulation Settings. (If this is a new simulation, enter the name of the profile and click OK. The Simulation Settings dialog box appears. 16. From the Analysis type list box, select Time Domain (Transient). 17. Specify the required parameters for the transient analysis need to run. 18. Click OK to save the simulation profile. 19. From Captures PSpice menu, choose Run to start the simulation when the simulation is complete, PSpice automatically displays the selected waveform.

EXPT 1 DC POWER SUPPLY DESIGN USING BUCK BOOST CONVERTERS AIM To Design the buck-boost converter for the given input voltage variation, load current and output voltage. Plot the regulation characteristics. APPARATUS REQUIRED Orcad 9.2 tool CIRCUIT DIAGRAM
V2 L1 1 0.75uh
V

12Vdc

V1

AC = TRAN = pwl(0 0 0.2u 0 0.20001u 5 0.4u 5 0.4001u 0) DC = R1 C1 D1

1k

1.2mf

1N4500

THEORY The primary advantage of switching-mode power supplies is they can accomplish power conversion and regulation at 100% efficiency -- given ideal parts. All power loss is due to less than ideal parts and the power loss in the control circuitry. In this section we explore some of the switching-mode power supplies that can be constructed using only one each of the parts from our simple parts list. The buck converter named as voltage step-down converter, current step-up converter, chopper, direct converter, et. Understanding its operation is basic to switching-mode power supply design. First let's turn on the switch and watch what happens to the output voltage versus time. For illustrative purposes we want the filter under-damped so we will decrease the load by increasing the load resistor from 0.25 ohms to 1.0 ohms. As shown in Figure the SPICE simulation waveform overshoots 12 V to 16 V and then has a damped ringing related to the filter resonant frequency (532 Hz) and final settles at 11.5 V, the input voltage. If the filter were unloaded, it would overshoot to 24 V (twice the input voltage) and would oscillate between zero and 24 V at a

frequency of 532 Hz. The turn-off waveform starts at 12 V and exponentially decays to zero volts without ringing. The cycle then starts again. OUTPUT WAVEFORM

RESULT Thus we designed the DC power supply design using buck-boost converter for the given input voltage variation, load current and output voltage and plotted the regulation characteristics.

EXPT 2 DC POWER SUPPLY DESIGN USING FLY BACK CONVERTER AIM To design the fly back converter using ferrite core transformer for the given input voltage variation load current and output voltage. APPARATUS REQUIRED Orcad 10.0 tool CIRCUIT DIAGRAM
L1 1 100uh
V

D1 1

BYW96E C2 100nf C3 0.47uf V2 V1 12v C4 100uf 12v R3 V 100k

0 0
M1

0
BUZ41A/SIE 8 2 4 5 6 7

0 0
U1

R4 220k

R1 1k

VCC TRIGGER RESET OUTPUT CONTROL THRESHOLD DISCHARGE GND 555B 1

3 R7 33k

R6 1k

Q2 BF471/PLP

R5 470

R2 10k

C1 2nf

THEORY For a transistor BUZ41A rated at maximum Vds=500 V and a resistance of 1.5 ohm at 4.5 A. The diode should be a fast switching type like BYW95C.The inductor is 100 H with a new tenths of an ohm series resistance capable of handling several amps of current. The main aspect of the circuit is how an ordinary 555 timer is used to regulate the output voltage. Without Rf and T1 the 1 frequency is f . 0.693( R2 2 R1 )C

With out any feed back the output voltage at this frequency will be in excess of 200v.However the voltage divider formed by R4,R2 and R7 has been designed and adjusted in such a way that when the output voltage reaches 180V,T1 just starts to conduct. When T1 starts to conduct it will pull down the internal supply voltage of this network resulting in a smaller voltage swing and hence higher frequency. In this way the output voltage will settle at a value determined by R7.The drawbacks of such simple controller is that the circuit has no protection at all against short circuit or overload situations. An accidental circuit of the output will therefore always result in a defect power transistor. OUTPUT WAVEFORM

RESULT Thus we designed the DC power supply design using fly-back converter for the given input voltage variation, load current and output voltage and plotted the regulation characteristics.

EXPT 3 DESIGN OF AC/DC VOLTAGE REGULATOR USING SCR AIM Design a phase controlled voltage regulator using full wave rectifier and SCR, vary the conduction angle and plot the output voltage. APPARATUS REQUIRED Orcad 9.2 tool CIRCUIT DIAGRAM

R1 2.2K X1 2N5060 V2 VOFF = 0V VAMPL = 5V FREQ = 250hz R2 1.5K D1 1 2

1N4500

R4 1k R3 120

THEORY The firing of SCR is controlled by UJT operated firing circuit. The diode bridge is in series with SCR and load. The diode bridge converts AC into pulsating DC. zener diode provides trapezoidal voltage across UJT circuit. At positive half C is changes through R until Vt reaches Vf (breakdown of UJT) At Ve=Vf UJT conducts and C discharges through small resistance Rb1 giving rise to a short steep current pulse Vg which in turn fires SCR. Due to finite time

constant RC there is always lag between power supply and SCR gate voltage determined by the value of R and C by varying R. Thus desired firing point at Q1 in half cycle is chosen. The shaded portion of rectified Vi waveforms indicates the region for which SCR is conductivity. Controlled rectifiers used in heavy duty power supplies with adjustable output voltage. This can be done for the control of the rectifier that it conducts only fraction of cycle. Then average value or DC component of rectifier output load voltages. SCR is used as controlled rectifier. It conducts several hundred of forward current and reverse current. OUTPUT WAVEFORM

RESULT Thus we Design a phase controlled voltage regulator using SCR, and plotted the output voltage.

EXPT 4 DESIGN OF PROCESS CONTROL TIMER AIM To design a sequential timer to switch on & off for at least 3 relays in a particular sequence using timer IC.
APPARATUS REQUIRED Orcad 10.0 tool CIRCUIT DIAGRAM
V2 R7 100k 8 U3

0
5Vdc R1 100k 1B 7 3 6 5 C2 0.01uf 10uf C1

R4 33k 4

U2 7 6 5

R6 100k

R5 33k 4

U1

RESET VCC DISCHARGE 2 TRIGGER THRESHOLD CONTROL OUTPUT GND 555alt 1

2 V3 DC = AC = TRAN = pwl(0 0 0.2u 0 0.20001u 5 0.4u 5 0.40001u 0)

RESET VCC DISCHARGE TRIGGER THRESHOLD CONTROL OUTPUT GND 555alt 1

RESET VCC 7 DISCHARGE 2 TRIGGER 6 THRESHOLD C3 5 4.7uf CONTROL 3 OUTPUT GND 555alt 1 C4 0.01uf

C5 10.7uf

C6 0.01uf

0
C8 C7 0.001uf 0.001uf

Fig 1 Sequential timer circuit

THEORY Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. The figure 1 shows a sequencer circuit with possible applications in many systems, and Figure 2 shows the output waveforms. A very practical application of the 555 timer is the generation of timing pulses for control purposes. The circuit illustrated in Fig. 1 shows a set of monostable pulse generators connected in series and parallel. After circuit reset the falling edge of input pulse Vin triggers the start of pulse sequence generation. The time duration of each monostable pulse is set by external capacitors.

OUTPUT WAVEFORM

Fig Sequential Timer Waveforms

RESULT Thus the design of sequential timer to switch on & off at least 3 relays in a particular sequence using timer IC was performed.

EXPT 5
PCB LAYOUT DESIGN USING CAD AIM To draw the schematic of simple electronic circuit and design of PCB layout using ORCAD. DESIGN STEPS 1. Schematic design 1.1. Creating a project To create a new project, 1. Launch Capture. (Start/programs/orcad10/capture CIS) 2. From the File menu, choose New > Project. 3. In the New Project dialog box, specify the project name. 4. To specify the project type, select Analog or Mixed A/D. 5. Specify the location where you want the project files to be created and click OK. 6. In the Create PSpice Project dialog box, select the Create a blank project option button. 7. Click OK to create the project with the above specifications. 1.2. Preparations in Capture Creating a flat design Adding parts To add parts to the design 1. From the Place menu in Capture, select Part. 2. In the Place Part dialog box, first select the library from which the part is to be added and then instantiate the part on the schematic page. 3. From the Part List, select the component and click OK. 4. Place the components on the schematic page as shown in the circuit and Rightclick and select End Mode. Connecting parts After placing the required parts on the schematic page, 1. From the Place menu, choose Wire. The pointer changes to a crosshair. 2. Add wires to the design until all parts are connected as shown in the circuit. 3. To stop wiring, right-click and select End Wire. The pointer changes to the default arrow. 2. Board design using ORCAD Layout To be able to take a design created in Capture to OrCAD Layouts, the tasks that are to be completed in OrCAD Capture are 1. Running DRC 2. Creating Layout netlist 2.1 Running DRC Before taking a design from a schematic editor to a board planner, run design rules check (DRC). This step is performed in OrCAD Capture.

To run DRC on the circuit design, complete the following steps: 1. In the Project Manager window, select the design file, *.dsn. 2. From the Tools menu, select Design Rule Checks. 3. In the Design Rules Check dialog box, the Design Rules Check tab is selected by default. Specify your preferences. By default, the Check entire design option button is selected. To run DRC on the complete design, accept the default selection. 4. Select the Use Occurrences option button. 5. To run the DRC, select the Check design rule option button. 6. In the Report section, select appropriate check boxes to specify what all is required in the DRC report. 7. Select the View Output check box. 8. In the Report File text box, specify the name and the location of the DRC file to be created. 9. Click OK. After the checks are done, the DRC report is displayed in the Format shown below. Checking Pins and Pin Connections Checking Schematic: *. -------------------------------------------------Checking Electrical Rules Checking for Unconnected Nets Checking for Invalid References Checking for Duplicate References Check Bus width mismatch 2.2 Creating Layout net list After running the Design Rule Checks, create the Layout netlist in Capture. 1. In the Project Manager window, select the design file, *.dsn. 2. From the Tools menu in Capture, choose Create Net list. 3. In the Create Net list dialog box, select the Layout tab. 4. In the Net list File text box, type *.MNL as the name for the layout net list to be created. 5 Click OK. 3. Creating a board Having created the layout net list, the next step is to create a new board in Layout. 3.1 Launch Layout From the Start menu, choose Programs >OrCAD 10.0 > Layout plus. Create the Layout board file While creating a new board file in OrCAD Layout, merge the electrical information from the layout net list (.MNL) and physical information from a template file (.TPL) or a technology file (.TCH) to create a new board design (.MAX).

1. From the File menu in OrCAD Layout, choose New. The AutoECO dialog box appears. 2. In the Input Layout TCH or TPL or MAX file text box, specify the name and the location of the technology file to be used for your board. we can either create our own templates or use existing ones. To view the existing technology files, click the Browse button. From the list of files, select 2bet_smt.tch and click Open. 3. In the Input MNL netlist file text box, specify the location of the *.MNL created in the Creating Layout netlist section. Note that the Output Layout MAX file text box, is automatically populated with the name and the location of the Layout board file, *.MAX. 4. From the drop-down list in the Options section, select AutoECO. 5. To create the Layout board file with the settings specified click ApplyECO. The Layout progress box appears indicating that the board file is being created. The process of creating a board file will be completed only if the footprint information is available for all the components in the design. 6. Once the AutoECO process is complete, the AutoECO dialog box appears with the report. To accept the changes, click the Accept this ECO button. 7. The AutoECO message box appears stating that the process is complete. Click OK. The layout board file, with components and the connectivity information appears. 3.2 Creating a board outline Layout requires one board outline on the global layer. The board outline defines the boundary of the board. To create a board outlines: 1 From the Tool menu, select Obstacle and then select New. 2 To insert the first corner of the PCB board, click the left-mouse button and draw the board outline. 3 Because a board outline must be a closed polygon, Layout automatically begins forming a closed area after the insertion of the first corner of the board outline, and automatically closes the polygon Continue clicking the left mouse button to insert corners. 4 Right-click and select Finish. Layout automatically completes the board outline. 3.3 Placing components

After created the board outline, start placing the components in the board. OrCAD Layout supports both manual placements and auto placements. Selecting components using mouse 1. From the toolbar, select the Component Tool button. 2. Select a component with the left-mouse button. The component attaches to the cursor. 3. Move the component to the desired location. 4. To release the component, right-click and select End 5. Press the <F5> key to refresh your screen. 3.4. Design rules check After placing the components using manual placements. Run a check to ensure that component placement has been done properly and there is no spacing violation. 1. From the Auto menu in Layout, choose Design Rule Check. The Check Design Rules dialog box appears. 2. Specify the checks that need to be run. 3. Clicks OK. Layout checks the board for violations and marks any errorswith circles. 3.5. Routing After completing the board placement, route the board to complete the electrical connections between components. OrCAD Layout supports both manual routing and Auto routing. The eneral use model is to first route the critical nets manually, lock them and then auto route the rest of the board. Auto routing using Layout OrCAD Layout supports auto routing of board, components, and DRC. Board auto routing implies that the nets on the complete board are routed. Component routing routes only the nets attached to the selected component. DRC routings implies that all the nets within the DRC box defined by the user are routed. To auto route a component 1 From the Auto menu, choose Auto route > Component. 2 Select the component that need to be routed. All the nets connected to that component are routed. Similarly, to automatically route a complete board, choose Board from the Auto route submenu. To auto route region choose DRC from the Auto route submenu. 3.6. Renaming components

After completed the placement and routing of the PCB board, the components can be renamed on the PCB board in a specific order. 1. From the Options menu, choose Components Renaming. The Rename Direction dialog box appears. 2. Select one of the renaming strategies. 3. Click OK. 4. From the Auto menu, choose Rename Components. Layout renames the components. The reference designators for the component on the board changes. 4. Generating output The final task in creating a board design is to generate output files. We can create Gerber files, drill files, DXF files, and printer/plotter files. Before generating the reports and the output files, clean up the design. To clean up the design 1. From the Auto menu, choose Cleanup Design. The Cleanup Design dialog box appears. 2. In the Cleanup Routing section, click the Select All button. 3. In the Cleanup Database section, select all three check boxes, to ensure that unused pad stacks, footprints, and Nets are removed. 4. Click OK. Message boxes appear indicating the cleanup process being performed. The desired output files and reports can be generated now. RESULT Thus we have drawn the schematic of simple electronic circuit and design of PCB layout using ORCAD.

EXPT 6 STUDY OF AMPLITUDE MODULATION AND DEMODULATION AIM To study the amplitude modulation and demodulation technique using a base modulator and to calculate modulation index. APPARATUS REQUIRED 1. 2. 3. 4. VCT-08 Trainer Kit. VCT-09 Trainer Kit Cathode Ray Oscilloscope Path Chords.

FORMULA TO BE USED ma = Vm/Vc ma = (Vmax Vmin) / (Vmax+Vmin) Where ma = Modulation index Vm = Maximum amplitude of modulating signal Vc = Maximum amplitute of carrier signal Vmax = Maximum variation of AM signal Vmin = Minimum variation of AM signal CIRCUIT DIAGRAM AM TRANSMITTER BLOCK DIAGRAM Modulating signal source Audi signal amplifier Modulating signal driver Antenna

Amplitude modulator RF Carrier Oscillator Buffer Amplifier Carrier Driver

Power amplifier

Coupling circuit

AM RECEIVER BLOCK DIAGRAM

RF Amplifier

AM Detector

Buffer And Filter

Audio Power Amplifer

Loud Speaker THEORY The audio amplifier stage has a BJT CE amplifier. The AM makes use of base modulation technique. This circuit is an RF oscillator. The telescopic whip antenna is used to radiate the am signal generated by the module. AM receiver is known as tuned radio frequency receiver which consists of two or three stages of RF amplifier. In the receiver RF amplifier stage has a tank circuit which can be tuned to desired frequency range of reception. The telescopic whip antenna picks up the RF signal from the air and it is coupled to RF amplifier and then to am detector, buffer, filter, audio power amplifier and then to loud speaker. PROCEDURE 1. The circuit writing is done as shown in the writing diagram. 2. A modulating signal input is given to the amplitude modulator from the onboard sine wave generator. 3. Modulating signal input to the amplitude modulator can also be given from an external function generator or an audio frequency oscillator. 4. If an external signal source with every low voltage level(below 100mV) is used then this signal can be amplified using the audio amplifier before connecting to the input of amplitude modulator. 5. The amplitude and the time duration of the carrier signal are observed and noted down from the output of the amplitude modulator by keeping the amplitude knob of the sinewave generator at zero position. 6. Now increase the amplitude of the modulating signal to the required level. 7. The amplitude and time duration of the modulating signal are observed using a CRO and tabulated. 8. Finally the amplitute modulated output is observed from the output of the amplitute modulated wave are plotted neatly.

9. Calculate the modulation index or depth of modulation by using the two formulate and verfy them. 10. Calculate the modulation index or depth of modulation by using and the two formulae and verify them. 11. Now this experiment can be repeated by changing the values of amplitude and frequency of the modulating signal and the carrier signal. PROCEDURE FOR DEMODULATION 1. The circuit wiring is done as shown in the wiring diagram given below. 2. An AM wave is generated and the waveform of this AM signal is viewed and plotted. 3. The AM output from VCT-08 is patched to the input of the amplitude detector of VCT-09 and also the ground terminals of VCT-08 & VCT -09 are to be patched without fail. 4. The detector output is patched to the input of the buffer and filter stage in order to remove the 50Hz power supply noise and also the high frequency. 5. The out put of the filter section is patched to the input of an audio power amplifier stage. 6. The final demodulated signal output is viewed using a CRO at the output of the audio power amplifier stages. Also the amplitude & time duration of the demodulation wave are noted down. 7. From the tabulated values the AM wave and the demodulated signal are plotted neatly. Note: this experiment can be repeated for different value of amplitude & frequency of the modulation & carrier signals. TABULATION FOR AM Signal Modulated Signal Carrier Signal Amplitude Modulated Wave Amplitude Vm= Vc= Vmax= Vmin= Time t1 = t2 = tm = tc = Frequency f1 = f2 = fm = fc =

TABULATION FOR DEMODULATION Signal Amplitude Modulated Signal Demodulated Wave Amplitude Vmax= Vmin= V= tm = tc = t = Time fm= fc = f = Frequency

MODEL WAVEFORM

CALCULATION ma = Vm/Vc ma = ma = (Vmax Vmin) / (Vmax+Vmin) ma = Percentage Modulation = ma * 100 RESULT The amplitude modulation and demodulation technique was studied and the depth of modulation was calculated. Also the waveforms were plotted nearly. Percentage Modulation = -------------

EXPT 7 STUDY OF FREQUENCY MODULATION AIM To transmit a modulating signal after frequency modulation using VCT -12 trainer and received that signal back after demodulating using VCT-13 trainer. APPARATUS REQUIRED * VCT -12 trainer * VCT -13 trainer * CRO * Patch cords CIRCUIT DIAGRAM FM TRANSMITTER BLOCK DIAGRAM Audio Oscillator

FM Modulator

Output Amplifier

Carrier Generator

FM RECEIVER BLOCK DIAGRAM

RF Amplifier

Mixer

IF Amplifier

AF Amplifier

Local Oscillat or

Discrimi nator

AF Amplifier

THEORY The frequency of the message is changed in accordance with the carrier signal. The advantages of the FM are that if any transmission is affected by electrical noise and this noise is super imposed with the transmitted signal, the bandwidth of the FM signal is very wide compared with AM. Frequency of operation is calculated by F=1/2LC.

PROCEDURE 1. The connections are given a per the circuit diagram 2. Modulating signal is given to the frequency modulator from the on board sine wave generator. 3. Modulating signal input for FM can also be given from external function generator 4. If an external signal source with low voltage level is used then this signal source causes amplification before connecting to the input of frequency modulation. 5. The amplitude and time duration of modulating signal is observed using the CRO. 6. Finally frequency modulated output is observed from the output of the trainer VCT 12 using CRO. 7. Patch the modulated signal to the antenna in the receiver trainer kit. 8. The demodulated Signal is obtained.

RESULT Thus a signal has been frequency modulated and recovered after demodulation.

EXPT 8 DESIGN OF WIRELESS DATE MODEM AIM To study FSK modulator and demodulator technique. APPARATUS REQUIRED * Wireless data modem trainer kit * Patch Cords *CRO THEORY FSK is one method used to overcome the bandwidth limitation of the telephone system so that digital data can be sent over the phone lines. The basic idea of FSK is to represent 1s and 0s by two different frequencies with in the telephone bandwidth. The standard frequency for a full duplex 300 band modem in the originate modes are 1070 Hz for a 0 (called a space) and 1270 Hz for a 1 (called a mark). In the answer mode, 2025 Hz is a 0 and 2225 Hz is a 1.The relationship of these FSK frequencies and the telephone bandwidth is illustrated in figure. Signal in both bands can exist at the same time on the phone line and they do not interfere with each other because of the frequency separation. Need For FSK in Modem In FSK, the carrier frequency is shifted in steps or level corresponding to the level of the digital modulation signal. In the case of a binary signal, two carrier frequencies are used. One corresponding to binary 0, and other to binary 1(i.e mark). Example is shown in fig. The baud rate is the number of change of the transmitted data. This can be determined by taking the reciprocal of the time of the shortest pulse transmitted. A low speed modem such as the one we are focusing on sends and receives serial data at a rate of 300 baud. For a 300 baud data stream, maximum frequency occur when the data stream has 0s and 1s alternatively and the frequency of this will be 150Hz. As mention earlier the telephone network has a bandwidth between 300Hz & 3000Hz. So the maximum frequency of 300 baud data stream falls out of the bandwidth range of the telephone lines. FSK modem is one method used to overcome the bandwidth limitation of the telephone network for digital data transmission. As mention earlier in FSK, the standard frequency for a space is either 1070Hz or 2025Hz depending on the modern mode and that of a mark is either 1270Hz or 2025 Hz. All these frequencies come under the permissible frequency range of the telephone lines. Thus the bandwidth limitation of the telephone lies is overcome by the uses of FSK.

HARDWARE DESCRIPTION OF VCT-10A Square wave

Serial data interface De bounce logic

FSK Modulator

RF Transmitter

RF Transmission The RF transmission used in VCT-10A, employ amplitude modulation of a 433.92MHZ carrier signal. The FSK signal is given as the input modulating signal to the RF trasmitter. The amplitude modulation radio signal is radiated using a telescopic whip antenna. HARDWARE DESCRIPTION OF VCT-10B

RF Receiver

FSK Demodulator

Serial Interface Serial data out

PROCEDURE 1. Patch the connections as per the block diagram. 2. Apply the input signal to the trainer. 3. Observe the output waveforms using the CRO. RESULT Thus the performance of Wireless data modem was studied.

EXPT 9 FREQUENCY MODULATOR AIM To design a frequency modulator circuit using OP-AMP LM 741 in Orcad 9.2. APPARATUS REQUIRED Orcad 9.2 CIRCUIT DIAGRAM
V2 C1 0.01uf V5 12v R3

12VdcU1
4

R2 2 1k -

OS1 OUT

R1 6 5 10k 2 LM741

V+

V-

LM741 1

20k U2 3

OS2

5 6 1
V

OUT V4

V+

OS2

OS1

V3
V

V4 12v

12v V1

0
VOFF = -5v VAMPL = 5v FREQ = 250hz

THEORY The frequency of the message signal is changed accordance with carrier signal. The advantages of frequency modulation are that if any transmission is affected by electrical noise and this noise is super imposed with the transmitted signal. The bandwidth of the FM signal is very wide compared with AM. PROCEDURE Connections are made as per the circuit diagram When the input signal is given to the circuit the output will be a square wave and it is given feed back to the integrator as input and after integration the resulting output will be a triangular wave. The modulated wave is the carrier wave for the modulating next input signal.

The frequency modulated wave is taken from the second op-amp.

OUTPUT WAVEFORM

RESULT Thus the frequency modulator was designed and the performance was studied.

EXPT 10 DESIGN OF FSK MODULATOR USING 555 TIMER AIM To design the frequency shift keying modulator using 555 timer APPARATUS REQUIRED Orcad 9.2 SPECIFICATIONS Resistor, Capacitor, 555 timer, Power supply CIRCUIT DIAGRAM
V2 12v 8 Q6 DSTM12 R1 50k Implementation = gh1 BC107A 2 4 5 6 7

U1

S1

R2 47k R3 50k

VCC TRIGGER RESET OUTPUT CONTROL THRESHOLD DISCHARGE GND 555B C1 1 .01u

3
V

.01u

THEORY In digital data communication binary code is transmitted by shifting a carrier frequency between present frequencies. This type of transmission is called frequency shift keying technique. A 555 timer is unstable mode which can be used to generate FSK signal. In the circuit the standard digital data input frequencies are off and 555 timer work in the normal astable mode of operation. The frequency of the output waveform 1.45 can be written as f 0 ( R A 2 R B )C

Frequency between 1090Hz and 1270 Hz is used as one of the signal PSK. When the input is low, the transistor goes to ON stage and connect the resistor (R0) across 1.45 R4.The output frequency is given by f 0 . R A RC 2 RB OUTPUT WAVEFORM

RESULT Thus the performance of FSK modulator using 555 timer was studied. Wireless data modem was studied.

EXPT 11 DESIGN OF INSTRUMENTATION AMPLIFIER USING OPAMP AIM To design the instrumentation amplifier using opamp. APPARATUS REQUIRED Orcad 9.2

V3
7

U2 V1 4v 2 LM741 3 4.000V +

V+

OS2

12Vdc 5 R1 6 1 6.000V
V

R3 1k

OUT
V-

1k

OS1

12.00V

4.000V 2 V4 12Vdc 2.000V R7 1k U3

V+

1k

82.85uV 3

U4

R5

-6.000V OS2 5 6 1
V

OUT R6 1k LM741 -12.00V 28.98uV

V-

OS1

V2 2Vdc

3 2.000V 2 LM741

V+

OS2 OUT

5 6 1

137.7uV

R2 1k

R4 1k

V-

OS1

0
4

0V

THEORY The following circuit is a three op-amps instrumentation amplifier with easy gain adjustment design. This circuit has the benefit of easy gain adjustment with only one control resistor. This circuit topology has been used inside a single chip instrumentation amplifier IC because of the easy gain adjustment feature. In this circuit, the differential gain can be changed simply by changing the value of Rgain. The lowest gain possible is achieved with Rgain completely open. This intimidating circuit is constructed from a buffered differential amplifier stage with three new resistors linking the two buffer circuits together. Consider all resistors to be of equal value except for Rgain. The

negative feedback of the upper-left op-amp causes the voltage at point 1 (top of Rgain) to be equal to V1. Likewise, the voltage at point 2 (bottom of Rgain) is held to a value equal to V2. This establishes a voltage drop across Rgain equal to the voltage difference between V1 and V2. That voltage drop causes a current through Rgain, and since the feedback loops of the two input op-amps draw no current, that same amount of current through Rgain must be going through the two "R" resistors above and below it. This produces a voltage drop between points 3 and 4 equal to:

The regular differential amplifier on the right-hand side of the circuit then takes this voltage drop between points 3 and 4, and amplifies it by a gain of 1 (assuming again that all "R" resistors are of equal value). Though this looks like a cumbersome way to build a differential amplifier, it has the distinct advantages of possessing extremely high input impedances on the V1 and V2 inputs (because they connect straight into the noninverting inputs of their respective op-amps), and adjustable gain that can be set by a single resistor. Manipulating the above formula a bit, we have a general expression for overall voltage gain in the instrumentation amplifier:

OUTPUT WAVEFORM

RESULT Thus the performance of instrumentation amplifier using opamp was studied. Wireless