BCD and Binary Adder/Subtractor

Awal dari penggunaan penguat operasional adalah tahun 1940-an, ketika sirkuit elektronika dasar dibuat dengan menggunakan tabung vakum untuk melakukan operasi matematika seperti penjumlahan, pengurangan perkalian dan pembagian integral dan turunan Istilah penguat operasional itu sendiri baru digunakan pertama kali oleh John Ragazzini dan kawan-kawan dalam sebuah karya tulis yang dipublikasikan pada tahun 1947. Dengan cepatnya perkembangan teknologi yang saat ini merupakan hal yang sangat berpengaruh baik dalam dunia sains, teknologi bahkan bisa masuk keranah ekonomi yang sangat pesat maka sekiranya kita perlu memahami tentang apa nama komponen yang digunakan dalam sebuah rangkaian elektronikaa dan bagaimana sistem aplikasi kerja dari alat tersebut untuk memahaminya perlu diadaka praktikum dengan baik agar dapat memahami dan membandingkan sebuah rangkaian hardware dengan simulasi. Tujuan 1) Mengerti dan memahami rangkaian adder dan subtractor 2) Mampu menganalisis cara kerja rangkaian adder dan subtractor Dasar Teori Penguat operasional (Op-amp = operasional amplifier) merupakan jenis penguat elektronika swngan sambatan (coupling) arus yang memiliki bati (faktor penguat) sangat besar dengan dua masukan dan satu keluaran, pada umumnya oenguat operasional tersedia dalam bentuk sirkuit terpadu dan yang paling banyak

As promising results have been obtained in defeating code obfuscation techniques, malware authors have adopted protection approaches to hide malware-related data from analysis. Consequently, the discovery of internal ciphertext data in malware is now critical for malware forensics and cyber-crime analysis. In this paper, we present a novel approach to automatically extract secrets from malware. Our approach identifies and extracts binary code relevant to secret hiding behaviors. Then, we relocate and reuse the extracted binary code in a self-contained fashion to reveal hidden information. We demonstrate the feasibility of our approach through a proof-of-concept prototype called ASES (Automatic and Systematic Extraction of Secrets) along with experimental results.

This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less delay and a smaller area size .Since this multiplication operation is for both signed and unsigned numbers,cost of the system can also be reduced. The carry save adder (CSA) tree and the final adder can speed up the operation of multiplier. Koggestone adder is a parallel prefix form carry look ahead adder .We determine that by replacing carry save adder(CSA) and final two operand parallel prefix adder with parallel prefix adders of koggestone algorithm reduces delay furthur more resulting in substantial increase in speed of circuits.

In this paper, we have designed the detailed logical circuits of 1-bit full adder- subtractor
working on analog inputs while manipulating it through half-adder, NAND, AND and OR gates integrating with ANN and Machine Learning algorithm where fixed bias is also applied with each of the designed logical gate combinations. Because hardware implementation is far better than the software manipulation so combination of designed circuit can be used to further design ANN based 4-bit or 8-bit full Adder Subtractor. Creating the new hardware device following the same circuits and techniques can reflect the best performance of Adder Subtractor over analog inputs. Resultant waveform of designed ANN based 1-bit full Adder-Subtractor and its subcircuits are completely in favor of its new hardware implementation.

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, called PAS-GH, is designed using the Feynman, Peres, and Fredkin gates. It decreases the number of garbage outputs and quantum cost. The transistor realizations of the CLA-GH and PAS-GH circuits are provided accordingly. The evaluation results indicate that the proposed circuits surpass the existing works in all figures of merit.

Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V + gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.