Application-Specific Processors

A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking textures that are applied to objects in the scene. To be useful, the generated noise should be repeatable while exhibiting no discernible periodicity, anisotropy, or aliasing. However, noise with these qualities is computationally expensive and results in a significant fraction of the run time for scenes with rich visual complexity. We propose modifications to the standard algorithm for computing synthetic noise that improve the visual quality of the noise, and a parallel hardware implementation of this improved noise function that allows the use of reduced precision arithmetic during the noise computation. The result is a special-purpose function unit for producing synthetic noise that computes high-quality noise values approximately two orders of magnitude faster than software techniques. The circuit, using a commercial CMOS cell library in a 65nm process, would run at 1GHz and consume 325µm × 325µm of chip area.

Different applications written in java are suitable to execute with different garbage collectors (GC's). In the current scenario the selection of a garbage collector depends on machine architecture and operating system. Serial collector is invoked for most of the application running on client class and parallel collector is invoked for applications running on server class. In this research paper we have proposed a solution for the intelligent selection and activation of garbage collector with appropriate parameters for finding the optimal performance for each benchmark of SPECjvm2008. The parameter settings which we have obtained after testing and analysis of data are used to decide the heap size and the GC for the benchmark. That setting would give optimal and best performance for that particular benchmark. The proposed model achieves improvement of 2% in throughput and also reduced the execution time of the application by 7% as compared to the default collector. It can also be used for the real time application because of the improved performance by reducing the frequency of collection. Garbage collection time is also reduced by 39%. Number of times the application stopped due to garbage collection is also reduced. Memory reclamation after garbage collection is also increased.

Modern platform-based design involves the application-specific extension of embedded processors to fit customer requirements. To accomplish this task, the possibilities offered by recent custom/extensible processors for tuning their instruction set and microarchitecture to the applications of interest have to be exploited. A significant factor often determining the success of this process is the utomation available in application analysis and custom instruction generation. In this paper we present YARDstick, a design automation tool for custom processor development flows that focuses on generating and evaluating application-specific hardware extensions. YARDstick is a building block for ASIP development, integrating application analysis, custom instruction generation and selection with user-defined compiler intermediate representations. In a YARDstick-enabled environment, practical issues in traditional ASIP design are confronted efficiently; the exploration infrastructure is liberated from compiler and simulator idiosyncrasies, since the ASIP designer is empowered with the freedom of specifying the target architectures of choice and adding new implementations of analyses and custom instruction generation/selection methods. To illustrate the capabilities of the YARDstick approach, we present interesting exploration scenarios: quantifying the effect of machine-dependent compiler optimizations and the selection of the target architecture in terms of operation set and memory model on custom instruction generation/selection under different input/output constraints.

This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotated image windows and their integral image windows for each classifier which perform parallel classification operations to detect non-upright (rotated) and non-frontal (profile) faces in the images. We use the training data from OpenCV to detect the frontal and profile faces based on the Viola and Jones algorithm. The proposed architecture for multi-view face detection has been designed using Verilog HDL and implemented in a Xilinx Virtex-5 FPGA. Its performance has been measured and compared with a Jones' and Viola's software implementation of multi-view face detection.