Advances in FPGA tools and techniques

Microprocessors and Microsystems 29 (2005) 47–49 www.elsevier.com/locate/micpro Editorial Advances in FPGA tools and techniques This Special Issue on FPGA Tools and Techniques collects high-quality state-of-the-art papers to provide a more comprehensive perspective of the FPGA tools that, nowadays, are being developed by the research community, along with the new FPGA techniques that are arising. FPGAs (Field-Programmable Gate Arrays) have experienced a radical change throughout the last few years, being, at present, very popular devices in many different areas. As a result, chip programmability has now reached a high level of sophistication. This increasing sophistication in FPGA devices is quickly forcing a change in the techniques and tools landscape. On the one hand, high-end FPGAs are requiring high-quality tools that optimize the internal functionality of the FPGA, facilitate their programmability using higher-level languages, and also provide a greater visibility into how the device will work in the final system. Many research groups from around the world are working on this kind of tools. On the other hand, as the reconfigurable computing is becoming an increasingly important computing paradigm, more and more FPGA techniques are appearing. FPGA devices are making it possible for thousands of computer engineers to have access to digital design technology in an easier way, obtaining a better performance with a similar flexibility to software. In addition, ASIC engineers are now ‘reconfiguring’ themselves as FPGA engineers for economic reasons and adding to the growing legions of FPGA designers. In conclusion, these new FPGA techniques are being enriched by both points of view, hardware and software, blurring the traditional frontiers between both. It is impossible to cover all the technical issues about FPGAs in only one Special Issue. Due to this fact and the high popularity of our call for papers (with more than 65 high-quality submissions from many different countries), we have prepared a series with three Special Issues on FPGAs. The first one (‘Special Issue on FPGAs: Applications and Designs’, Microprocessors and Microsystems, vol. 28, nos. 5–6, August 2004) introduces some of the most important aspects about FPGAs and shows the current impact of these devices, which are already accelerating a vast range of applications. In fact, the papers in this first Special Issue prove that FPGAs are a good alternative for many real applications in image and signal processing, 0141-9331/$ - see front matter q 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.micpro.2004.06.003 multimedia, robotics, telecommunications, cryptography, networking and computation in general. On the other hand, this second Special Issue is focused on FPGA tools and techniques. Therefore, this issue does not pay attention to the many applications of FPGAs to other fields, but to the existing utilities for the FPGA engineers. As we are going to see, many research groups are working on the development of new tools in order to make easier the programming, optimisation, debugging and evaluation of FPGA-based systems; while other groups are interested in the design of new techniques for fabricating FPGAs, improving the CLB (Configurable Logic Block) structure, testing components of FPGAs, etc. Finally, the third Special Issue, which will appear later this year, will be devoted to a deeper analysis of some case studies. More exactly, case studies in the area of computer vision and image processing, a very important area of application for FPGAs. In conclusion, for this current Special Issue we have selected six papers that cover a spectrum of significant FPGA tools and techniques. The topics covered in the papers are timely and important, and the authors have done an excellent job of presenting the material. We are sure this issue will be very useful for all the readers who are engaged in the many issues surrounding FPGAs. The title of our first paper is ‘Automatic Mapping of C Computations to FPGAs with the DEFACTO Compilation and Synthesis System’, by P. Diniz, M. Hall, J. Park, B. So, and H. Ziegler. This paper clearly shows the importance and need of high-quality tools that facilitate the FPGA programming by means of higher-level languages. To make programming of FPGA-based systems more accessible, the authors have developed the DEFACTO system. This system offers a high-level imperative programming paradigm, such as C, coupled with new parallelizing compiler technology oriented towards FPGA designs. In this way, FPGA designers retain the advantages of a simple computational model via a high-level language but rely on powerful compiler analyses to automate most of the tedious and error-prone tasks. Using DEFACTO, key computational components of the algorithm are executed in custom hardware designs on FPGAs, while the remaining computation and coordination with FPGAs are performed in software on an external host. The authors illustrate 48 M.A. Vega-Rodrı́guez et al. / Microprocessors and Microsystems 29 (2005) 47–49 the efficiency of their approach with the automatic mapping of a set of five image-processing and multimedia applications. With the growing number of available transistors in future FPGA devices and the increasing time-to-market pressures, the need to quickly generate a correct design with good performance will make high-level design tools such as DEFACTO extremely attractive. The second paper, ‘System-Level Performance Evaluation of Reconfigurable Processors’ by R. Enzler, C. Plessl, and M. Platzner, treats the development of high-quality tools for optimizing the internal functionality of the FPGAbased systems. More concretely, the authors present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. A hybrid reconfigurable processor is a platform that combines a field-programmable device (mainly, an FPGA) with a general-purpose CPU. These platforms have received increasing attention in the last years. However, the design of a hybrid reconfigurable processor involves a multitude of design decisions related to finding an optimal architecture of the reconfigurable unit (RU) and a suitable system integration of the CPU and the RU. And, therefore, determining the impact of these design decisions on the overall system performance is an important and challenging task. The authors show the effectiveness of their framework discussing, as an example, a hybrid processor for datastreaming applications that attaches a coarse-grained reconfigurable unit to the coprocessor interface of a CPU core. Furthermore, using FIR filters as a case study, the authors evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. In summary, we can state that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. Our third paper ‘Microprocessor and FPGA Interfaces for in-System co-Debugging in Field Programmable Hybrid Systems’ authored by M.A. Aguirre, J.N. Tombs, V. BaenaLecuyer, J.L. Mora, J.M. Carrasco, A. Torralba, and L.G. Franquelo, presents issues related to the design of tools that provide greater visibility into how the device will work in the final system. The authors explain how a hardware debugger can be made for a general-purpose hybrid system. These systems consist of a software part running on a microprocessor or DSP, and a hardware part represented by an FPGA. The co-debugging of the hybrid hardware– software system consists in the resolution of two key problems, the observability and the controllability, during execution time. As result, the authors describe their experience acquired with the platform UNSHADES-2, which has been designed with special-purpose hardware resources to support the debugging task. UNSHADES-2 is a powerful platform that can produce sufficient information about the execution system even without stopping the system. In this way, a system can be monitored while working a full system speed, thus allowing optimisations of certain design characteristics in real world situations. As conclusion, this paper shows that it is possible to make meaningful debugging measurements from a hybrid system. This can lead to a deeper understanding of the system being debugged, and opens the possibility to perform intensive post-failure studies of the system when an unexpected result is produced. Wire routing is a key problem in Electronic Design Automation (EDA) for VLSI integrated circuits. An FPGA technique to design an effective hardware accelerator for maze routing is addressed in the fourth paper, ‘L3: An FPGA-Based Multilayer Maze Routing Accelerator’ by J.A. Nestor. The algorithms followed for the maze routing are computationally expensive, and the use of an FPGA accelerator can speed up the routing process by taking advantage of potential parallelism in the algorithms, using an array of processing elements (PEs). Even when the connection distance is small, the proposed technique still provides significant acceleration over software since the algorithm in software requires multiple memory accesses, which can consume thousands of processor clock cycles. Additional features of this technique include support for rapid removal of obstacles and connections as required by routers that use a ‘rip up and reroute’ strategy, and support for preferential routing on a layer-by-layer basis. In conclusion, an interesting technique that can be efficiently implemented using an FPGA. The fifth paper (‘Pseudo Online Testing Methodologies for Various Components of Field Programmable Gate Arrays’ by L.K. Kumar, A.S. Ramani, A.J. Mupid, and V. Kamakoti) describes novel pseudo online Built-In Self-Test (BIST) based techniques for detecting and locating multiple faults in Look-Up Tables (LUTs), interconnections and dedicated clock lines of FPGAs. These techniques use the partial reconfiguration capabilities of modern FPGAs, and find extensive applications in safety critical systems like space probes, which comprise several subcircuits mapped onto the FPGA and employ online checkers to report misbehaviour of any of these subcircuits. When an online checker reports misbehaviour of one such subcircuit, the techniques proposed in this paper attempt to detect and locate the faults, if any, within the faulty subcircuit without shutting down the other subcircuits. In addition, the techniques presented by the authors preserve the routing structure of the configured application in-place. This is crucial for the non-faulty parts of the system to continue working while the faulty portion is being tested, so that either the system can be made fail-safe or made to continue working with a lesser performance. The last but not the least important paper in this Special Issue, ‘A 5-10 GHz SiGe BiCMOS FPGA with New Configurable Logic Block’ by C. You, J.-R. Guo, R.P. Kraft, M. Chu, P. Curran, K. Zhou, B. Goda, and J.F. McDonald, presents a new multiplexer-based FPGA, which can operate at a clock frequency of 5–10 GHz. M.A. Vega-Rodrı́guez et al. / Microprocessors and Microsystems 29 (2005) 47–49 Redundant switches on the original signal paths are removed improving the performance. The configurable logic block’s (CLB’s) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. Furthermore, a new CLB structure is presented greatly increasing the routing capability, and including more inputs/outputs in each direction. In order to prove this approach, a chip consisting of four FPGA ring oscillators has been fabricated, and the Spice simulation results and chip measurements are presented. In conclusion, this paper brightens the future of multiplexer-based FPGAs by converting conventional CMOS multiplexers to BiCMOS multiplexers, and adding new structures and capabilities. We sincerely hope that you enjoy this Special Issue. We also have hope that the paper collection as a whole can pleasantly introduce the readers to the composite and challenging arena of FPGA tools and techniques, and can help in giving a fresh perspective of several state-of-the-art solutions in the field. We extend our sincere thanks to all the authors who submitted papers for this Special Issue and the many reviewers, whose dedicated efforts made this Special Issue possible. Miguel A. Vega-Rodrı́guez*, Juan M. Sánchez-Pérez, Juan A. Gómez-Pulido Departamento de Informática, Universidad de Extremadura Escuela Politécnica, Campus Universitario, s/n, 10071 Cáceres, Spain E-mail addresses: [email protected], [email protected], [email protected] Received 15 June 2004 Available online 21 July 2004 *Correspondingauthor.Tel.: C34-927-257-263; fax: C34-927-257-202. 49 Miguel A. Vega-Rodrı́guez is Professor of Computer Architecture in the Department of Computer Science, University of Extremadura, Spain. He received a PhD degree in Computer Science from the University of Extremadura. Dr Vega-Rodriguez’s main research interests are FPGAs in customcomputing applications, applications of reconfigurable hardware to image processing and cryptography, and cache memory systems on multiprocessors. Juan M. Sánchez-Pérez is Professor of Computer Architecture in the Department of Computer Science, University of Extremadura, Spain. He received a PhD degree in Physics from the University Complutense of Madrid in 1976. His research interests are applications of reconfigurable hardware, logic design and modern computer architectures. Juan A. Gómez-Pulido is Professor of Computer Architecture in the Department of Computer Science, University of Extremadura, Spain. He received a PhD degree in Computer Science from the University Complutense of Madrid in 1993. His main research interests are applications of reconfigurable hardware to different fields of signal processing.