The Clear-PEM Electronics System

2704 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 5, OCTOBER 2006 The Clear-PEM Electronics System Edgar Albuquerque, Pedro Bento, Carlos Leong, Fernando Gonçalves, João Nobre, Joel Rego, Paulo Relvas, Pedro Lousã, Pedro Rodrigues, Isabel C. Teixeira, João P. Teixeira, Luís Silva, M. Medeiros Silva, Andreia Trindade, and João Varela Abstract—The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of 1 million events per second with an efficiency above 95%, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach. I. INTRODUCTION REAST cancer is reportedly among the deadliest. Studies show that one out of every eight women will develop breast cancer along her lifetime [1]. In 85% to 90% of the cases, the patient can fully recover, if the cancer is detected in its early stage. As a consequence, cancer early detection is recognized worldwide as a priority in health care. However, the detection sensitivity of present diagnosis systems is low. As an example, X-ray detection sensitivity is, in the less favorable cases, around 50% [2]. These cases refer to dense breasts, where it is difficult B Manuscript received October 20, 2004; revised November 20, 2005. This work was supported by Innovation Agency (AdI) and Operational Program for Information Society (POSI), Portugal. The work of P. Rodrigues and A. Trindade was supported by FCT by Grants SFRH/BD/10187/2002 and SFRH/BD/10198/2002. E. Albuquerque, P. Bento, and C. Leong are with INESC-ID, Lisboa, Portugal. F. Gonçalves, I. C. Teixeira, J. P. Teixeira, and M. Medeiros Silva are with INESC-ID, Lisboa, Portuga. and also with IST—Instituto Superior Técnico, Universidade Técnica de Lisboa, Portugal. J. Nobre, J. Rego, P. Relvas, P. Lousã, and L. Silva are with INOV, Lisboa, Portugal. P. Rodrigues and A. Trindade are with LIP—Laboratório de Instrumentação e Física Experimental de Partículas, Lisboa, Portugal (e-mail: Joao.Varela@cern. ch). J. Varela is with LIP—Laboratório de Instrumentação e Física Experimental de Partículas, Lisboa, Portugal. He is also with CERN, Geneva, Switzerland and the IST—Instituto Superior Técnico, Universidade Técnica de Lisboa, Portugal. Digital Object Identifier 10.1109/TNS.2006.881650 to distinguish between the tumor and the normal tissues. Therefore, it is easy to understand that new diagnosis processes and systems for this type of cancer are the object of heavy research efforts. One such research line relies on the use of Positron Emission based technology. This is the case in the development of the Clear-PEM scanner, a high-resolution Positron Emission Mammography (PEM) system, capable of detecting tumors with diameters down to 2 mm [3]. Early stage breast cancer detection can be performed through functional PET imaging, where a localized increase of metabolic activity in breast tissue may indicate the presence of a neoplasm before the morphological changes detectable by standard mammography techniques take place. Because of the small dimensions of these lesions, a few millimeters in diameter, a detector system for such application must have high sensitivity and good spatial resolution. In this paper, some aspects of the Clear-PEM electronic system architecture are described. A major challenge of the work to be carried out is the huge amount of data that must be processed at the electronic level and sent afterwards to a computer for image reconstruction [5], [6]. An aspect that deserves serious consideration is the need to keep the examination time as short as possible. These constraints require the electronic system to be as efficient and as accurate as possible. To achieve this purpose, the data acquisition electronics (DAE) makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system is designed to sustain a data acquisition rate of 1 million events per second, with efficiency above 95% for pure photoelectric events, at a total single photon background rate of 10 MHz. These parameters have been validated with extensive Monte Carlo simulations, carried out using different models of the breast and different examination scenarios as described elsewhere [4]. These studies indicate a single photon rate of the order of 10 MHz in the most unfavorable cases, whereas the coincidences rates are below 40 kHz. The design value of the maximum data acquisition rate was chosen so that the same system can be used in future PET applications with higher rates. II. CLEAR-PEM DETECTOR SYSTEM The Clear-PEM detector system for positron emission mammography is being developed by the PEM Consortium within the framework of the Crystal Clear Collaboration at CERN [4]. It consists of two parallel detector heads each one holding 96 detector modules. Each module is composed of a 2 2 20 mm LYSO:Ce crystal array, optically coupled on each side to avalanche photodiodes (APDs) to allow depth of interaction determination [4]. Thus, in total, there are 12 288 readout channels. Beyond the Clear-PEM detector, the electronic system functionality is partitioned into front-end electronics, 0018-9499/$20.00 © 2006 IEEE ALBUQUERQUE et al.: CLEAR-PEM ELECTRONICS SYSTEM 2705 Fig. 1. Clear-PEM electronics system overview. Front-end electronics planes A and B are connected, respectively, to the top and bottom APDs of the crystal layer in one PEM Detector Head. Front-end electronics planes C and D have identical connections in the second Detector Head. Fig. 2. Block diagram of the amplifier and multiplexer chip. coupled to the detector heads, and off-detector trigger and data acquisition electronics. These are crucial components in the Clear-PEM scanner, since the performance of these system components is decisive to achieve high detection sensitivity and low acceptance of background noise. A. System Top-Level Architecture The higher-level architecture of the PEM system under development is represented in Fig. 1. Four front-end electronic blocks are responsible for analog signal detection, each one directly connected to the top (bottom) of one plane of crystals. Amplifiers and analog multiplexer integrated circuits [application specific integrated circuit (ASIC)], and analog-to-digital converters (ASCs) are the main constituting components in the front-end blocks. Digital signal cables connect the front-end blocks to the off-detector electronics, referred to as DAE, which includes the trigger and data acquisition circuits. Off-detector electronics is implemented in a standard crate system. After processing, data is sent to a PC for image reconstruction. B. Front—End Electronic System The front-end electronics performs the readout of 6144 crystals, 3072 per detector plate. Each side of the crystal matrix coupled to a 32-pixel Hamamatsu S8550 APD array is connected to a low noise charge amplifier and multiplexer chip. This chip performs the readout of one side of six modules (total of 192 channels), amplification, sampling, and storage in analog memories at 100 MHz, and selection of two active channels (192:2 multiplexing) above a common threshold (see Fig. 2). The capability of selecting two channels allows the exploitation of two-hit Compton events and, therefore, increases the scanner 2706 sensitivity. The common threshold is set above the noise level and is the same for all 192 channels on each ASIC. The chip operates in data-driven synchronous mode, such that the output samples have fixed latency relative to the input pulse. This simplifies the front-end circuit with respect to the requirements of a coincidence trigger with good time resolution. No dedicated trigger signal is generated by the front-end system, which would require sophisticated discriminators. Instead, the trigger information is extracted from the main data flow in the off-detector system. On the other hand, a synchronous design avoids the need for time tagging of data pulses in the front-end chip. Each analog data frame is composed of 10 samples (from to sample ) and is stored in analog memories. sample The first sample above the common threshold is considered as sample 0, and the amplified pulse has a peaking time of about 30 ns. Therefore, the data frame may contain 2 to 4 presamples. The presamples are used by the off-detector electronic system for pedestal estimation and correction, on an event-by-event basis. If three or more channels are found active in a 100 ns interval, i.e., two channels are already transmitting two data frames and a request is made to transmit a third data frame, an error code is produced indicating that a front-end overflow condition has occurred. The output multiplexing can be a source of inefficiency, due to pile-up of signal events with background photons. However, because the signal width is 100 ns and the photon background rate per chip is at maximum in the order of 300 kHz [4], the pile-up probability is kept below 4%. The analog samples are digitized in the front-end by 10-bit sampling ADCs running at 100 MHz. The digital data are serialized in low-voltage differential signaling ( LVDS) bit streams and transmitted to the off-detector system. The transmission of 10-sample data frames per detector pulse to the trigger and data acquisition system allows more flexibility in adapting the trigger algorithms, implemented in programmable logic, to new requirements. C. Data Acquisition System The data acquisition system is implemented in a set of boards housed in a 6U crate. One generic bus and one dedicated trigger bus with two channels are used for data exchange. Two types of electronic boards are used, namely the data acquisition boards (DAQ boards) performing deserialization, temporary data storage, and algorithmic processing, and the trigger and data concentrator board (TGR/DCC Board) that selects events in coincidence, and interfaces to the data acquisition computer. An event is defined as relevant if it corresponds to the simultaneous occurrence of hits in both crystal planes. In this context, simultaneous means within the same discrete time window. The photon interaction time is determined by a pair of parameters-time tag/delta. Time tag is the time of occurrence of the largest sample in the pulse, and delta is the time interval (phase) between the time tag and the peak of the analog pulse. In Fig. 3 the top-level model of the data acquisition electronics system is depicted. As can be observed, the system functionality is implemented using field programmable gate arrays (FPGAs). The system functionality is distributed among eight FPGAs that implement the data acquisition (DAQ FPGA) IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 5, OCTOBER 2006 and one FPGA that implements trigger and data concentration (TRG/DCC FPGA). Three types of modules can be identified in each DAQ FPGA, namely, DAQ-four per FPGA, Filter-one per FPGA, and DAQ read out controller (DAQ ROC)-one per FPGA. Four main modules can be identified in the TRG/DCC FPGA, namely, the Trigger module, the TRG/DCC ROC, the DCC , and the DCC ROC. The DAQ FPGAs are the first processing elements in the trigger and data acquisition system. Each FPGA receives digital data frames, each one with 10 samples, from eight front-end ASICs, corresponding to the one trigger region (one-fourth of a detector head including top and bottom APDs). The major functions of the DAQ modules are: computation of the amplitude and time of the digitized detector pulses, validation of crystal hits matching the top and bottom crystal identifiers, and identification of the occurrence of photoelectric hits in one crystal. The energy sum of hits in crystals of a trigger region, found within a programable time window (called Compton window), is also compared to the event energy threshold. Specifications include the requirement that the system parameters should be online configurable. These parameters are the energy thresholds used to identify photoelectric and Compton hits, the Compton Window, that is, the time interval used to identify the Compton hits that may belong to the same event, and the Coincidence Window. Another requirement is that the set of constants used to calibrate crystals, photo sensors, and amplifiers characteristics be online configurable. One subset of these constants is used to perform energy calibration, and the other constants are used for time calibration. The equations used for evaluation of Delta and Energy associated with the photoelectric or Compton events are (1) (2) (3) In these equations, Sample (3) is the highest energy sample, (1) is the first sample in the pulse rising edge, and and are the presamples of the set. S are the set of sample values after pedestal subtraction. The subscript (1,2) indicates whether these samples are associated with the top or bottom side of the crystal plate. The first equation normalizes the energy value and also estimates the pedestal and removes it. Of the two data frames per crystal, that with highest amplitude is used to compute Delta. As aforementioned, in order to minimize dead-time the trigger and data acquisition architecture makes extensive use of pipeline processing and derandomizer memories with multi-event capacity. The trigger algorithms are decomposed into sequences of elementary operations executed in pipeline ALBUQUERQUE et al.: CLEAR-PEM ELECTRONICS SYSTEM 2707 Fig. 3. Top-level model of the data acquisition electronics system. mode. Multiple sequences corresponding to the various input data streams are processed in parallel. The main function to be carried out by the DAQ ROC is to organize and to prepare the data coming from the DAQ modules, via Filter, to the generic bus. Moreover, the DAQ ROC is used to load the constant parameters into the DAQ modules. DAQ ROC receives those parameters from the PC through the PCI Bus. It also accumulates the number of errors that occur at the DAQ modules, and sends them to the PC upon user request. In the Trigger module (TRG/DCC FPGA), a search for twophoton events in true coincidence or random coincidence is performed. For the detection of true coincidence events, the Trigger compares the Time Tag/Delta of hits in both detector planes and if the time difference is less than the Coincidence Window the event is accepted. For the random coincidence a similar procedure is used, in which the time information on one of the hits is subjected to an adjustable delay. In each case, a trigger signal occurs and the TRG/DCC board notifies the other boards that the corresponding data must be processed and sent to the PC for image processing. A flag written in the event header is used to distinguish between real and random coincidences. A trigger on single photon events is also implemented for calibration purposes. At each trigger, complete data frames (10 digitized samples) of the identified detector hits are transmitted to the data acquisition PC via a PCI-to-PCI link with a throughput of 400 Mbyte/s. This allows for the off-line recomputation of the energy and time of detector hits using more sophisticated algorithms. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates (Xilinx Virtex II), eight FPGAs corresponding to the DAQ modules and a ninth FPGA that implements the Trigger/DCC modules. All FPGA modules where designed and simulated, demonstrating that the required 100–MHz operation frequency can be achieved. Results are presented in Section III of this paper. At present, the hardware test of the FPGAs is being carried out in parallel with the development of the crate backplane and boards. D. Modeling and Simulation Framework The Clear-PEM detector will operate under several imaging scenarios. Each of these scenarios presents a radiation environment that varies from patient to patient, for different anatomical regions (breast or axilla) or configurations (standard or frontback). Each of these cases will correspond to different acquisition rates, raw data volumes, and spatial resolutions. Therefore, detailed simulations of the Clear-PEM detector and trigger 2708 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 5, OCTOBER 2006 Fig. 5. Two-stage amplifier. Fig. 4. Overview of the modeling and simulation framework. system are necessary in order to understand the trigger performance, optimize electronics configuration parameters, and evaluate its impact on the performance of energy, time, and position reconstruction algorithms. No less important is the capability to produce realistic data sets that will be used to study the FPGA design, assess the hardware implementation, and evaluate the influence of the data acquisition system on the reconstructed images. For these tasks a simulation framework has been implemented which is partitioned in three functional modules (see Fig. 4). The two first modules were developed using the Geant4 Monte Carlo simulation toolkit [8]. They include the simulation of radioactive decay and photon tracking in phantoms of the upper torso and breast (PhantomFactory module), as well as the detector response (PEMsim module) [4], [6], [7]. The last application, DIGITsim, is a high-level simulation of the signal generation and information processing in the front-end and DAE system. The first module, PhantomFactory, allows the description of both mathematical and voxel-type phantoms. Radioisotope decay is simulated, and the resulting decay products are tracked through the geometry. Photons that reach a predefined scoring region are stored for latter tracking. The simulation of the interaction of photons with the Clear-PEM scanner is performed by the PEMsim module, using data from the PhantomFactory module. The input to DIGITsim is contained in the data stream produced by PEMsim, and includes, for each event (photons that interact with the detector): deposited energy in each crystal, interaction point, associated time-of-flight, reference tag to the initial PhantomFactory event, and crystal identification. The major functional blocks of DIGITsim are (Fig. 4, B1 through B4): B1. Production of a transient container, that contains time slices. The number of time slices is a function of the simulated radioisotope activity. All events with times belonging to time slice are grouped into a single mixed event. Each mixed event is then used as the starting point for the digitization chain. B2. Translation of the detector hits information (energy, position, and time) into a parameterized pulse shape. Reproduction of the photodetector and front-end electronics chain (crystals, APDs, amplifiers, multiplexing, and A/D conversion). B3. Simulation of trigger logic for each valid data frame. B4. Simulation of the DCC data stream output. In order to perform realistic simulations of the detector electronics several functional features were considered: dead-time due to the analog memory readout cycle (100 ns); either correlated or noncorrelated noise models; control of crystal light yields, APD pixel, and amplifier gains stored in a MySQL database; storage and retrieval of on-line trigger calibration constants. III. RESULTS A. Front-End Amplifier Simulation The current pulse produced by the APD has a very sharp rise (2–3 ns) and an exponential decay with a time constant ns; the pulse peak value has a maximum value of 0.75 A. The front-end amplifiers must produce an output voltage pulse ns, a peak value V when with a peaking time A) the input current has its maximum amplitude ( and a decay time of about 100 ns. Two basic approaches are used in front-end amplifiers for radiation detectors: charge-sensitive and voltage-sensitive amplifiers. The first approach has the advantage that the pulse shaping can be made independent from the circuit parasitics, but, in our case, a charge-sensitive amplifier cannot produce the required low peaking and decay times. Thus, a voltage-sensitive amplifier was adopted. In order to have the required output pulse amplitude the amplifier must have a high gain (of the order of 10 ), and to have the required peaking time it must have a high bandwidth (above 10 MHz). Thus, a high gain-bandwidth product is required (exceeding 10 GHz), which cannot be obtained with one gain stage. Thus, a two-stage amplifier must be used. Different 2-stage amplifier circuits have been considered and simulated. The best results in terms of stability and noise have been obtained with the architecture of Fig. 5. The amplifier and are simply a NMOS commonblocks with gains source circuit followed by a NMOS source follower. ALBUQUERQUE et al.: CLEAR-PEM ELECTRONICS SYSTEM 2709 Fig. 8. Organization of the DAQ FPGA VHDL test bench. voltage source). Increasing the width of the input transistor has a limit, since this leads to increased capacitances and reduced bandwidth. Fig. 6. Output voltage pulse for different input charges. B. DAQ FPGA Unit Tests Fig. 7. Output voltage peak value as a function of the total input charge, for input pulses with an exponential time constant  = 40 ns. The amplifier has been designed with the 0.35 m CMOS technology of AMS designated by C35B4C3. In this technology, there are four metal layers, two low resistivity poly (polysilicon) layers, and one high-resistivity poly (this is required to realize resistors with high resistance values). In Fig. 6, we show the simulated output voltage pulse for different amplitudes of the input current corresponding to charges with values between 3 and 34 fC. In Fig. 7, we represent as a function of : the slope is 26.7 mV/fC and there is up to 1.1 V. The peaking time is reasonable linearity for about 30 ns, which satisfies the specifications. The equivalent noise charge (ENC), obtained by simulation taking into account the capacitance of the APD (10 pF), is . Noise reduction is obtained by designing the amplifier with a wide input transistor (the noise contribution from this transistor is dominant, and it should have a high transconductance to minimize the equivalent input noise In this section, the validation tests of the DAQ FPGA design, implemented in a VHDL [9] test bench (hardware model) and in DIGITsim are described. The primary objective consists in the validation of time and energy extraction algorithms since these constitute the kernel of the digital data stream processing and provide the primitive information required for the trigger decision by the TRG/DCC board. Results obtained with these two methods were compared at bit-level, to assess the correctness of the algorithms implementation. The following strategy has been followed (Fig. 8): events produced by the PhantomFactor y/PEMsim modules were interfaced with DIGITsim, and a list of digitized data frames was obtained (two for each hit). Each data frame corresponds to the information sent by the front-end system (Fig. 4, B2) after the A/D conversion, and contains 10 samples plus “Monte Carlo truth” variables energy and phase. These last ones are obtained at the level of PEMsim and, therefore, do not account for the influence of the electronics system. The same list of samples was used as stimuli to the VHDL test bench and DIGITsim DAQ Simulator. For each event, DAQ FPGA VHDL and DIGITsim values of reconstructed energy and phase where compared with the “Monte Carlo truth” values. Table I shows the comparison for a set of 10 single events (pure photoelectric or two-hit Compton). A perfect agreement between the two outputs was found. “Monte Carlo truth” energy values were converted from keV to 10-bit integer using the E [keV]. Energy and phase values relation: E calculated with the VHDL and DIGITsim simulation show a good agreement with the original energy and time, confirming the suitability of these algorithms for the on-line trigger. C. Energy and Time Extraction Algorithms DIGITsim was used to assess the performance of the energy and time extraction algorithms implemented in the DAQ VHDL model. Hits between 50 and 511 keV for several amplifier noise and APD gain scenarios were considered. Figs. 9 and 10 present single-photon time (FWHM in ns) and energy (FWHM/Average) resolution. For an amplifier noise of 950 e ENC and an APD gain of 102, the energy and time 2710 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 5, OCTOBER 2006 TABLE I COMPARISON OF ENERGY (10-BIT)/PHASE (8-BIT) PAIRS FOR EACH HIT RECONSTRUCTED BY THE DAQ FPGA VHDL AND DIGITSIM WITH THE “MONTE CARLO TRUTH” INPUT VALUES Fig. 11. Ratio simulated over reconstructed energy as a function of the phase between the highest sample and the peak of the analog pulse. Fig. 12. Energy resolution for pulses with fixed and random phase relative to the sampling clock. Fig. 9. Time resolution as function of deposited energy for four different values of amplifier noise and APD gain. Fig. 10. Energy resolution (FWHM/Average) as function of deposited energy. resolutions for 511 keV are 10% and 470 ps, respectively. For 100 keV, the energy and time resolution are of the order of 36% and 2 ns. The energy and single-photon time resolution values include the photoelectron statistical fluctuation, APD excess noise factor and electronics noise, but do not include the intrinsic nonuniformities of the LYSO crystal and the contribution from the scintillation light statistical noise to the pulse shape. Fluctuations in the input charge pulse will be responsible for changes in the amplifier output pulse structure, namely on the pulse peaking times. This will lead to a degradation of the time and paramextraction algorithm (2) response, since eters are computed assuming a constant peaking time for each readout channel. The influence of these parameters is under study and it is estimated to be about 1–1.5 ns single-photon time resolution at 511 keV. The single-photon time resolution depends critically on the signal-to-noise ratio, as illustrated in Fig. 9. An improvement of this parameter may be achieved by increasing the APD gain. Tests are under way to determine whether the S8550 APD can be operated safely at a gain of the order of 100–200. Figs. 11 and 12 show the effect of the random phase of the sampling clock relative to the analog pulse in the energy determination. The highest sample, used to estimate the pulse energy, is larger than 98% of the peak amplitude for all phase values, as shown in Fig. 11. The energy resolutions for pulses with fixed and random phase relative to the sampling clock are compared in Fig. 12, showing a small degradation of the resolution due to the phase effect. ALBUQUERQUE et al.: CLEAR-PEM ELECTRONICS SYSTEM D. DAE System Performance The simulation was also used to evaluate the efficiency and purity of the trigger system in various operating conditions. The efficiency for pure photoelectric coincidence events (one hit in each crystal plate) was found to be 96% for a threshold of 150 keV. The efficiency for a data sample that includes two-hit Compton events is 83%. Purity, defined as the fraction of events that are badly reconstructed (fakes or ghosts), is 14%. Ghost events are events with high-multiplicity (more than 3 hits in the same plate, which should be discarded on-line) that are converted into lower-multiplicity events due to rejection of low-energy Compton hits by the front-end (below the common threshold) or DAE system (poor quality time measurement). This also introduces fake events, in which the reconstructed event has a different topology from the initial one. For example a two-hit event can be transformed in a fake single-hit photoelectric event because the low-energy Compton hit was rejected. IV. SUMMARY AND FUTURE DEVELOPMENTS In this paper, an overview of the Clear-PEM electronics system architecture, as well as the design and implementation of the analog and digital components of the system were presented. Simulation results of the front-end chip and DAE system show that the fundamental requirements in terms of time resolution and trigger efficiency are fulfilled with the developed architecture. A DAQ FPGA VHDL model was concluded and 2711 verified against DIGITsim with a 100% agreement at bit-level for the outputs of the energy and time extraction algorithms. The validated model will be used to perform the final hardware synthesis of the DAQ VHDL in Xilinx Virtex II FPGAs. After synthesis, the same front-end data will be used to benchmark and develop a built-in-self-test to be included in the DAQ FPGAs. Next steps include the validation of the TRG/DCC VHDL model using as input the DAQ FPGAs DIGITsim output and the test of the front-end chip. REFERENCES [1] A. Jemal, Cancer Statistics 2004.. , CA: Cancer J Clin, 2004, vol. 54, 8–29. [2] P. A. Newcomb and P. M. Lantz, “Recent trends in breast cancer incidence, mortality, and mammography,” Breast Cancer Res. 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