Numerical evaluation of the ITRS transistor scaling

J Comput Electron (2015) 14:192–202 DOI 10.1007/s10825-014-0638-0 Numerical evaluation of the ITRS transistor scaling Roland Nagy · Alex Burenkov · Jürgen Lorenz Published online: 4 November 2014 © Springer Science+Business Media New York 2014 Abstract Predictions of the ITRS were evaluated using state-of-the-art numerical TCAD simulations. For this purpose, first a physically based simulation model was calibrated to reproduce published experimental results for CMOS transistors with a gate length of 20 nm. Then, the same physical model was applied for the numerical simulation of CMOS devices as specified by the ITRS for the years 2011–2026 with physical gate lengths scaled from 24 to 5.9 nm. Simulations of this work indicate that the quantum electron depletion at the interface between the silicon and the gate oxide strongly limits the CMOS transistor performance. To compensate the negative impact of the quantum depletion effect, a more aggressive gate-oxide scaling is suggested. Keywords ITRS · Bulk-silicon · SOI · Double-gate MOSFET · Scaling · DIBL · Sub-threshold slope 1 Introduction The International Technology Roadmap for Semiconductors (ITRS) [1] attempts to specify device performances which should be obtained within the next 15 years, and the research work required to achieve this goal. The relation between CMOS transistor scaling and performance was for a long period of time smooth and did not require a significant change of device architecture. Now, for the period of time considered in the 2011 edition of the ITRS [1], three device architectures R. Nagy · A. Burenkov (B) · J. Lorenz Fraunhofer Institute for Integrated Systems and Device Technology, Schottkystrasse 10, 91058 Erlangen, Germany e-mail: [email protected] R. Nagy e-mail: [email protected] 123 are suggested: the bulk silicon, ultra-thin-body single-gate SOI, and multi-gate CMOS transistor architectures. The introduction of new and more complicated transistor architectures is an attempt to overcome several parasitic physical effects that limit the CMOS transistor performance at nano-scale gate lengths. A basic problem at small gate lengths that limit the device performance is the short channel effect [2] which manifests itself in an increase of the inverse sub-threshold slope S and of the drain induced barrier lowering (DIBL). Further, the effect of quantum mechanical depletion of the charge carriers near the silicon-to-gateoxide interface [3–5] works like an increase of the effective gate-oxide thickness. This leads to a worsening of the electrostatic control of the electron transport in the channel and results also in an increase of the inverse sub-threshold slope S and of the DIBL. A significant negative impact on CMOS device performance comes also from the parasitic contact resistances [6–8]. However, there are also some physical effects that enhance the performance of CMOS transistors at nano-scale channel size. For example, the scattering on phonons is partly suppressed in nano-scale channels and, therefore, electrons move more like ballistic. The ballistic effect [9–11] enlarges the possible maximum velocity that can be attained by the electrons in an electric field. This can potentially increase the saturation current in nano-scaled CMOS transistors. Also the application of mechanical stress to the channel [12,13] is a common means to enhance the performance of nanotransistors. The interplay of these positive and negative impacts on the device performance determines the actual performance of the devices at each CMOS technology generation. There are several overviews on the development of the CMOS transistor performance along with the plans and predictions of the ITRS [14–16]. However, the question about the relationship of the results of numerical simulations J Comput Electron (2015) 14:192–202 using state-of-the-art TCAD to the plans of the ITRS has not been considered in the literature. In this work we analyze by means of numerical simulations the performance of CMOS devices scaled in accordance with the specifications of the ITRS, elucidate the differences between the ITRS roadmap and predictions from numerical TCAD simulations, elucidate the problems of gate scaling at nanoscale and suggest on the basis of the simulation results technological solutions for achieving the ambitious ITRS goals on CMOS device performance for future transistor generations. 193 Table 1 Basic NMOSFET parameters taken from the PIDS2 table of the 2011 ITRS Roadmap [1] Bulk MOSFET Year 2011 L G [nm] 24 20 17 14 E O T : TO x [nm] 0.88 0.79 0.67 0.55 x j [nm] 10 8 6.4 5 9 1018 [cm−3 ] 2013 2015 2017 4.5 6 7.7 VD D [nm] 0.9 0.85 0.8 0.75 I On [mA/µm] 1.319 1.422 1.582 1.774 2015 2017 2019 NA Single-gate FD SOI FET Year 2013 2 Physically-based simulation model We used Sentaurus TCAD [17] of Synopsys for the numerical simulation of CMOS transistors specified by the ITRS. In the first simulation runs, geometrical sizes and channel doping of the CMOS transistors were used as specified by the ITRS [1]. For simplicity, a uniform doping of 3 × 1020 cm−3 was used in the source and drain regions and the source/drain regions were aligned to the edges of the gate with zero overlap. The uniform doping in the source/drain regions of rectangular shape simplifies the comparison of the numerical results of this work with analytical models that use the same or similar simplified doping distributions. Basic geometrical and doping parameters of the n-channel transistors specified by the ITRS are illustrated in Table 1 which is a excerpt from the PIDS2 table of 2011 update of the ITRS. In the simulations, transistor parameters from the full version of the 2011 ITRS PIDS2 table that covers the time range from 2011 to 2026 were used. The model for the numerical simulation of the electron transport is based on the solution of the drift-diffusion equations in Sentaurus Device [17]. The charge carrier mobility model includes the effects of doping dependence [18], of the lateral electric field dependence due to surface roughness and due to surface and bulk phonon scattering [19] and the effect of the electron and hole velocity saturation at high electric fields [20–22]. The effect of the quantum depletion of the charge carriers in silicon near the silicon-to-gate-oxide interface was accounted for using the modified local density approximation (MLDA) [4,5]. The numerical simulation model was calibrated by a comparison of the simulation results with the results of electrical measurements [23] on CMOS transistors with a gate length of 20 nm. Two parameters were used as fitting parameters in the model calibration. The first parameter is the junction depth of the source and drain regions x j . This parameter along with the gate-oxide thickness strongly impacts the electrostatics of the transistors and therefore has a large impact on the subthreshold behavior characterized by the inverse sub-threshold slope S and the DIBL coefficient. L G [nm] 20 17 14 11.7 TO x [nm] 0.84 0.76 0.68 0.58 TSi [nm] 6.6 5.2 4.1 3.3 0.1 1018 [cm−3 ] 6 7.7 9 VD D [nm] 0.85 0.8 0.75 0.71 I On [mA/µm] 1.475 1.591 1.717 1.847 2015 2017 2019 2021 NA Multi-gate FET Year 2023 L G [nm] 17 14 11.7 9.7 8.1 TO x [nm] 0.8 0.72 0.65 0.59 0.53 TSi [nm] 11.3 9.4 7.7 6.3 5.2 1018 [cm−3 ] 7.7 9 0.1 0.1 0.1 VD D [nm] 0.8 0.75 0.71 0.66 0.62 I On [mA/µm] 1.627 1.744 1.857 1.975 2.087 NA Assuming correctness of the device models used, x j was extracted from the comparison of the simulated and measured transfer characteristics in the sub-threshold region for a gate length of 20 nm: It was adjusted in the simulations in order to reproduce the experimental values of the inverse subthreshold slope S and of the DIBL coefficients of the bulksilicon NMOSFETs implemented and measured at Samsung et al. [23]. The value of the junction depth x j for the bulk silicon n-channel transistor at 20 nm was found to be a factor 0.5 lower than the specifications of the ITRS presented in Table 1. Also for other gate lengths source/drain junction depths x j that are a factor of 0.5 lower than the ITRS specifications were used in the simulations of bulk silicon transistors. The thickness of the silicon body TSi which in SOI MOSFETs plays a similar role as x j in bulk silicon transistors was in some simulation variants also modified in this work in comparison to the ITRS specifications. To achive the required low values of S and DIBL, a value of 60 % of the ITRS specifications had to be assumed in numerical simulations for the silicon body thickness of the single-gate fully depleted and 123 194 Fig. 1 Comparison between the transfer characteristics of 20 nm NMOSFETs simulated with the calibrated model of this work (Sim.) and measurements from Samsung et al. (Exp.) [23] for double-gate SOI MOSFETs. It should be noted that x j and TSi are listed in the PIDS2 table of the 2011 ITRS as equivalent parameters, and there is no separate specification for the junction depths for the single-gate SOI and multi-gate MOSFETs. The second parameter that was fitted in the model calibration was the electron saturation velocity vsat , extracted from the electrical current-voltage characteristics at high drain voltages. The electron saturation velocity in large-size bulk silicon is equal to 1.07 × 105 m/s. In the channels of nanotransistors with gate lengths between 5 and 25 nm the saturation velocity is enhanced due to a suppression of certain interactions with phonons. Besides, the saturation velocity can also be enhanced due to application of mechanical stress. Both effects are relevant for the transistors considered, and it is difficult to separate them from each other. Therefore, we consider vsat as a model fitting parameter in this work and find the value of vsat from the comparison of the simulation results with the particular implementation of the CMOS transistors with a gate length of 20 nm reported by Samsung et al. [23]. Figure 1 demonstrates a good agreement between the calibrated simulation model and the experimental measurements of transfer characteristics of the NMOSFET [23] with a gate length of 20 nm. There may be a discussion about the dependence of the saturation velocity on the gate length [9–11], but in fact there are two opposite processes in effect leading correspondingly to an increase and to a decrease of vsat during the scaling of the gate length. If we consider the effect of the reduction of phonon scattering, the vsat should grow with a reduction of the gate length. On the other hand side, there is a ballistic Shur-effect [24] expected in nano-transistors, resulting in a reduction of the mean saturation velocity in the transistors with shorter gate lengths. Also mechanical stress which is typically used in advanced MOSFETs to enhance their 123 J Comput Electron (2015) 14:192–202 Fig. 2 Depth profile of the electron density in the on-state of a bulksilicon MOSFET with a gate length of 14 nm simulated with two models: with the quantum depletion effect (MLDA) and without it (Classical) performance changes the dispersion relations for the electrons and therefore can influence vsat . If we assume that the enhancement of the saturation velocity due to mechanical stress compensates its reduction due to the Shur-effect for the shortest gate lengths considered, a constant vsat independent of the gate lengths can be used in all simulations. This assumption is made in the following, because no better data were available. Specifically, we used the value of vsat = 2.5 × 105 m/s obtained from the model calibration for NMOSFETs with a gate length of 20 nm [23], mentioned above. Using this enhanced value of the saturation velocity we account in the simulation for two important effects: for the ballistic velocity saturation enhancement and partially also for the effect of current enhancement due to mechanical stress. Another important effect in nano-scale transistors is the effect of quantum depletion of the charge carriers near the silicon-to-gate-oxide interface. This effect is illustrated in Fig. 2 by a comparison of the electron density distributions simulated in the middle of the channel of the bulk-silicon NMOSFET with a gate length of 14 nm using two approximations, the classical simulation method and the quantum mechanical method of the modified local density approximation (MLDA). The electron density in the classical approximation has the maximum at the silicon surface. In contrast, the application of the quantum mechanical method of MLDA for the bulk-silicon MOSFET exhibit a depletion of the electron density towards the silicon surface under the gate. If the effect of quantum depletion is accounted for, the maximum of the electron current density in the inversion layer is not on the surface as in the classical case but is located at a depth of about 0.25 nm. This quantum mechanical effect of pushing-out the electron density from the silicon surface is equivalent to a reduction of the gate-to-channel capaci- J Comput Electron (2015) 14:192–202 195 tance that plays an important role for the performance of the nano-scaled transistors. A lower gate-to-channel capacitance reduces the electrostatic control of the gate over the channel charge and in this way reduces the device performance. 3 Simulation results 3.1 Bulk silicon transistor architecure 3.1.1 Drain current simulation results for bulk silicon MOSFETs First, we simulated the drain current in the bulk-silicon MOSFET with the geometrical and doping parameters as specified by the ITRS [1] for each physical gate length. In Fig. 3, the line with square symbols represents the ITRS goal for the on-state current. Option B1 shows the on-state drain current simulated with Sentaurus TCAD using the physical model explained before with the transistor parameters as specified by the ITRS. The results of the numerical simulations performed with geometrical and doping parameters as suggested by the ITRS do not predict a constant improvement of the on-state drain current as required for the bulk-silicon transistors with scaled gate lengths. Instead, the on-state drain current remains approximately at the same level when the gate length is scaled from 24 to about 15 nm. Only for a gate length of 14 nm there is some current enhancement due to gate scaling. The reason for such a bad scaling behavior of the bulk-silicon MOSFETs at these gate lengths in the simulation is twofold: First, the effect of quantum depletion works like an addition of a thickness of about 0.4 nm to the gate-oxide thickness specified in the ITRS as the equivalent oxide thickness (EOT) and reduces the on-current. Fig. 4 Scaling plans for the equivalent oxide thickness for bulk-silicon MOSFETs according to the ITRS Table 1 (ITRS Scaling) and according to a suggestion of this work (Modified Scaling) Second, the channel doping level enhancement as suggested by the ITRS for the scaled bulk-silicon MOSFETs reduces the on-current due to mobility reduction in heavilydoped channels. In Fig. 3 (Option B2) we also show the simulation result for the on-current scaling for the case of a constant channel doping of 5 × 1018 cm−3 . The required enhancement of the on-current could be achieved by this measure down to gate lengths of 18 nm. At smaller gate lengths, constant doping does not help to achieve the ITRS specifications on the on-current. Finally, if we combine the constant doping level in the channel with a more aggressive scaling of the gate oxide as shown in Fig. 4 as Modified Scaling, we obtain the required on-currents in the numerical simulation (Option B3). The suggested EOTs are at most 0.1 nm thinner than the suggestions of the ITRS, but this small change in EOT makes a large difference in transistor performance. In fact, high-kdielectrics are used as gate-oxide material in advanced nanoscaled transistors, therefore the difference of 0.1 nm in EOT results in an about 3 to 4 times larger difference in the thickness of the high-k-gate-isolation. The minimum required EOT of below 0.5 nm can in practice only be achieved using high quality high-k-dielectrics with a high dielectric constant so that the physical high-k-oxide thickness is larger than 1 or 2 nm to prevent tunneling through the gate isolation. 3.1.2 DIBL and sub-threshold slope simulation results for bulk silicon MOSFETs Fig. 3 On-state drain current specified by the ITRS Table 1 for bulksilicon MOSFETs in comparison with the results of numerical simulations using different scaling assumptions (Options B1 to B3) The DIBL and the inverse sub-threshold slope S are two electrical performance parameters impacted by the short channel effect that will be addressed in this paper besides the oncurrent. Option B1 in Fig. 5 presents the numerically simulated DIBL coefficient for the bulk-silicon MOSFETs scaled 123 196 Fig. 5 Comparison of scaling options for the drain induced barrier lowering (DIBL) for bulk-silicon NMOSFETs J Comput Electron (2015) 14:192–202 is scaled further to 15 nm. Finally, a slight increase of both coefficients is observed for 14 nm in comparison to 15 nm. The maximum values of DIBL and S are seen at 18 nm gate length for both the ITRS scaling and for the optimized scaling as suggested in this work. From Figs. 5 and 6 it follows that the MOSFETs have a worse performance at 18 nm gate length compared with 17 and 20 nm. Analyzing the simulation results, we found that the change of scaling trend for the 18 nm transistors is due to a particular choice of the EOTs in the ITRS for the bulk silicon MOSFETs with gate lengths between 14 and 24 nm. Summarizing the results obtained with the improved scaling strategy, we get all in all an advantage in the scaling of the transistors with an improved scaling strategy that combines more aggressive gate-oxide scaling and disregarding the channel doping increase for smaller gate lengths. With the optimized scaling parameters in EOT and channel doping we achieve a high drain current as required by the ITRS specification and a suppression of the short channel effects for shorter gate lengths. 3.2 Single-gate silicon-on-insulation (SOI) transistor architecure Fig. 6 Comparison of scaling options for the inverse sub-threshold slope for bulk-silicon NMOSFETs according to the ITRS specifications. The range of the DIBL coefficient values is from 68 to 98 mV/V. Option B3 in Fig. 5 shows the DIBL coefficient obtained for the MOSFETs that uses a more aggressive gate-oxide scaling (Fig 4, Option B3) and a constant doping level in the channel as for MOSFETs defined by Option B2. We can see that the more aggressive gate-oxide scaling and a constant doping in the channel (Option B3 in Fig. 5) result in lower DIBL values than those obtained for MOSFETs scaled as recommended by the ITRS. In Fig. 6 we show the numerically simulated inverse subthreshold slope and observe the same effect of improvement of the transistor sub-threshold performance resulting in a lower value of S for more aggressive gate-oxide scaling. Both parameters DIBL and S have a similar dependence on the transistor gate length. They continuously increase when scaling from 24 to 18 nm gate length, have a maximum value at 18 nm gate length, then decrease when the gate length 123 The ITRS [1] suggests to use single-gate SOI MOSFETs from a gate length of 20 nm in 2013 until 10.6 nm gate length in 2020. The main advantage of the SOI transistors in respect to the bulk-silicon transistors is a better suppression of the short channel effects. There are also lower drain and source capacitances in SOI-based transistors due to the buried-oxide isolation. This leads to a lower power consumption in the SOI based transistors. 3.2.1 Drain current simulation results for the single-gate SOI MOSFETs In Fig. 7 the ITRS target for the on-state drain current of the single-gate SOI n-channel MOSFETs that should be achieved in the result of the MOSFET scaling is presented. The ITRS specifies a continuous increase of the on-state drain current at a constant drain leakage current of 100 nA/µm during the gate length scaling. The numerical simulation performed for the SOI NMOSFETs with doping and geometrical parameters including the silicon body thickness TSi specified by the ITRS (Option S1) delivers an almost constant on-current when scaled from 20 to 14 nm gate length. There is a big jump to higher on-currents from 14 to 13 nm gate length, and the high on-current remains about constant for gate lengths in the range from 11 to 13 nm. The reason for this jump between 13 and 14 nm gate length is the discontinuous change of the channel doping in the ITRS table. According to the ITRS, channel doping is constant at a level of 1 × 1017 cm−3 for 13 nm gate length and smaller, but for larger gate lengths J Comput Electron (2015) 14:192–202 Fig. 7 On-current scaling plans for different scaling scenarios of the single-gate SOI MOSFETs: ITRS Target is the on-current specified according to the ITRS, Option S1 is the result of TCAD simulation for single-gate SOI MOSFETs scaled as specified by ITRS, Option S2 uses TSi = 0.6 × TSi (I T R S), Option S3 is as S2 but with a constant channel doping of 1 × 1017 cm−3 , Option S4 is as Option S2 but with a constant channel doping of 1 × 1015 cm−3 , Option S5 is as Option S2 but with a channel doping of 2.5 × 1018 cm−3 plus EOT scaling as shown in Fig. 8 for Option S5 doping is much higher and reaches 9 × 1018 cm−3 at a gate length of 14 nm. The sudden change of the doping concentration between transistors with 13 and 14 nm gate lengths leads to a jump in the on-state drain current. Obviously, the predicted ITRS curve for the on-state current (ITRS Target) and the numerically simulated (Option S1) on-state drain-current curve in Fig. 7 differ significantly. The problem is that the numerically simulated on-state current shown in Fig. 7 does not show any improvements due to the gate-length scaling until the jump at 14 nm. To obtain the expected performance improvements for scaled transistors, it is necessary to find a new way for the scaling of the SOI MOSFET. The first simulation experiment was to reduce the silicon body thickness from the value suggested by ITRS scaling to 60 % of the ITRS value. The on-state drain current resulting for this option is shown in Fig. 7 as Option S2. Using scaling of Option S2 the on-state-current is higher in comparison to Option S1 for all gate lengths, but the current jump at L = 14 nm remains. The third simulation experiment (Option S3) used a constant value for the channel doping of 1 × 1017 cm−3 for all gate-lengths. In the result, we obtain a drain current which is higher than the drain current expected by the ITRS, but there is almost no increase of the current for smaller gate lengths. Further, we tried to choose a lower channel doping of 1 × 1015 cm−3 to further maximize the drain current. Option S4 in Fig. 7 depicts the drain current obtained in this simulation experiment. The current at lower channel doping of 1 × 1015 cm−3 is in fact the same as with a channel 197 Fig. 8 Scaling plans for the equivalent oxide thickness for single-gate SOI MOSFETs according to the ITRS Table 1 (Option S1) and according to a suggestion of this work (Option S5) doping of 1 × 1017 cm−3 . This leads us to the conclusion that there is no improvement of the on-state current due to a lowering of the channel doping from 1 × 1017 cm−3 to 1 × 1015 cm−3 in SOI MOSFETs. The observed enhancement of the on-current in case that channel doping was lowered from the levels between 6×1018 cm−3 to 9×1018 cm−3 to the level of 1 × 1017 cm−3 and the absence of the enhancement when the doping level is further reduced from 1 × 1017 cm−3 to 1 × 1015 cm−3 indicates that the electron scattering on ionized doping impurities is not a dominant process if the channel doping concentration is equal or below 1 × 1017 cm−3 . With a lowering of the doping level in the channel the carrier scattering on the charged doping impurities may be diminished but other electron scattering mechanisms such as the scattering on surface roughness and phonon scattering remain and limit the on-state current. As it follows from the simulation results presented in Fig. 7, we can obtain even better on-currents as planned by the ITRS by using a constant channel doping of 1 × 1017 cm−3 or less. To reproduce the performance parameters of MOSFETs as planned by the ITRS, we can in the case of the single-gate SOI-based MOSFETs relax the requirements on the scaling of the gate-oxide thickness at larger gate lengths for achieving the ITRS performance goals as it was done in Option S5, Fig. 7. Figure 8 shows the scaling of the gate-oxide thickness suggested by the ITRS (Option S1) and the modified gate-oxide scaling (Option S5) as suggested in this work to reproduce numerically the on-state current of the SOI-based MOSFETs specified by the ITRS. Our numerical simulations show that the more aggressive gate-oxide scaling (Option S5) with a constant channel doping of 2.5 × 1018 cm−3 would lead to the on-state drain currents specified by the ITRS. 123 198 Fig. 9 Comparion of different scaling options for the DIBL effect for single-gate SOI NMOSFETs J Comput Electron (2015) 14:192–202 S3 in addition to the TSi reduction includes a constant doping of 1 × 1017 cm−3 in the channel for all gate lengths. Finally, Option S5 additionally uses somewhat relaxed gateoxide thicknesses for larger gate lengths and smaller gateoxide thicknesses in comparison to the ITRS specifications for smaller gate lengths as shown in Fig. 8. Changing scaling plans for the doping and for the gate-oxide scaling both influence the DIBL (Fig. 9) but the relaxation of the gate-oxide thickness for the gate lengths of 18 and 20 nm leads to DIBL values somewhat higher than 100 mV/V. The lowest DIBL values were achieved in scaling Option S2 at a gate length of 17 nm. In Fig. 10 the inverse sub-threshold slope of the transfer characteristics for the NMOSFETs is presented. The scaling Options S1, S2, S3 and S5 in Fig. 10 have the same meaning as in Fig. 9.The scaling options considered result in a similar dependence of the sub-threshold slope from the gate legths as the DIBL dependence shown before. Option S1 that numerically simulates the scaling according to 2011 ITRS results in significantly higher S values in comparison to the expected values below 100 mV/dec. The reduction of the silicon body thickness reduces the inverse sub-threshold slope S significantly. The effect of the gate-oxide scaling modification used in Option S5 is as expected: lower S for small gate lengths and higher S for higher gate lengths in comparison to Options S2 and S3. 3.3 Double-gate transistor architecure Fig. 10 Comparion of different scaling options for the inverse subthreshold slope: single-gate SOI NMOSFETs 3.2.2 DIBL and sub-threshold slope simulation results for single-gate SOI MOSFETs In Figs. 9 and 10, the DIBL and the inverse sub-threshold slope for single-gate SOI MOSFETs are depicted. The tolerable values for DIBL are expected to be below 100 mV/V. The ideal inverse sub-threshold slope of well designed MOSFETs is 60 mV/dec. at room temperature, but also S values up to 100 mV/dec. are tolerable. Option S1 in Fig. 9 shows the numerically simulated values of DIBL for transistors with doping and geometrical parameters including the thickness of the silicon body TSi as specified in the ITRS Table 1 with the DIBL values ranging from 163 until 188 mV/V. The obtained DIBL values for all gate lengths are too high to be tolerable. In Option S2, the silicon body thickness TSi was reduced to 60 % of the ITRS values. In the result, DIBL was reduced drastically to values of about 100 mV/V or below. Option 123 3.3.1 Drain current simulation results for the double-gate MOSFETs The double-gate MOS-transistor architecture is taken in this work as an example of the multi-gate MOSFET architecture envisaged by the ITRS. The specifications of the ITRS for the on-current of the multiple-gate NMOSFETs are presented in Fig. 11 by the curve marked ITRS Target. Option D1 is the on-state drain current obtained by numerical simulation for double-gate MOSFETs with the doping and geometrical scaling parameters including the silicon body thickness as specified by the ITRS. There is no improvement of the on-state current at the constant drain leakage current of 100 nA/µm due to scaling obtained in this simulation. Obviously there is a big gap between Option D1 and the target of the ITRS shown in Fig. 11. We tried to reduce this gap improving transistor scaling scenarios. The main reason for the low on-state current of the doublegate NMOSFETs was found in the too thick silicon body of about TSi = L/1.5 assumed in the ITRS tables for multigate MOSFETs. Therefore, we radicaly modified the scaling of the silicon body thickness for double-gate NMOSFETs assuming TSi = L/2.5. This resulted in a significant J Comput Electron (2015) 14:192–202 199 Fig. 13 Scaling scenarios for the drain induced barrier lowering (DIBL) for double-gate MOSFETs Fig. 11 Scaling plan for the on-state drain current specified by the ITRS (ITRS Target) for double-gate MOSFETs in comparison with the results of numerical simulations using different scaling assumptions (Options D1 to D4) Fig. 14 Scaling scenarios for the inverse sub-threshold slope for double-gate MOSFETs Fig. 12 Scaling scenarios for the equivalent oxide thickness for double-gate nMOSFETs according to the ITRS Table 1 (Option D1) and according to a suggestion of this work (Option D3) increase of the on-state currents for all gate lengths (Option D2 in Fig. 11). To ensure the planned increase of the on-state currents at smaller gate lengths, we modified the gate-oxide scaling in addition to the scaling of the silicon body thickness as shown in Fig. 12, Option D3. Option D1 in Fig. 12 presents the equivalent gate-oxide thickness as specified by the ITRS in Table 1. The modified EOT scaling resulting from our numerical simulations is shown as Option D3 in Fig. 12 and leads in simulations to the drain current values shown in Fig. 11 (Option D3) very close to the ITRS specifications. Additional simulation experiments show that a further reduction of the channel doping to a level of 1×1015 cm−3 did not lead to an enhancement of the drain on-current (Option D4, Fig. 11). 3.3.2 DIBL and sub-threshold slope of double-gate MOSFETs Option D1 in Figs. 13 and 14 presents TCAD simulated DIBL and inverse sub-threshold slope parameters, respectively, for double-gate MOSFETs with geometrical and doping parameters as specified by the ITRS in Table 1. The double-gate MOSFET devices scaled according to Option D1 with geometrical parameters from the ITRS Table 1 exhibit very large DIBL values in excess of 200 mV/dec and also rather high S values in the range from 87 to 102 mV/dec. The scaling Option D2 in Fig. 13 with reduced silicon body thickness of TSi = L/2.5 results in much lower DIBL values of about 75 mV/dec and in correspondingly lower inverse sub-threshsold slope (Option D2 in Fig. 14). Option D3 in Fig. 13 included additionally a more aggressive gate-oxide scaling as shown in Fig. 12. And finally Option D4 tested the effect of a lower channel doping. The 123 200 J Comput Electron (2015) 14:192–202 doping level was reduced from 1 × 1017 cm−3 in Option D3 to 1 × 1015 cm−3 in Option D4. The reduction of the channel doping below 1 × 1017 cm−3 does not improve significantly the performance parameters of the double-gate MOSFETs. The weak effect of the channel doping reduction means that the electron scattering on ionized impurities is a secondary order effect for the MOSFETs with channel doping below 1 × 1017 cm−3 . A reduction of the DIBL and S values with a reduction of the gate length from 17 to 8 nm in Options D3 and D4 is due to the more aggressive scaling of EOT in these scaling plans in comparison to the ITRS. 4 Comparison of MOSFET device architectures Figure 15 summarizes the optimized simulation results on the on-state drain current from the Figs. 3, 7 and 11. The gate-length dependence of the on-state drain current simulated in this work and presented in Fig. 15 for the bulk-silicon, single-gate SOI, and double-gate NMOSFETs is very similar for all three device architectures considered. This is not surprising because such behavior of the on-current is actually the goal of the device development envisaged by the ITRS. The simulation only confirmes that such a device development is possible, but it is possible only with a necessary modification of some of the geometrical and doping parameters in comparison to those as specified initially by the ITRS. The following figures illustrate which transistor parameters have to be modified during the transistor scaling to obtain the on-current scaling plan as presented in Fig. 15. From the results of our simulations it follows that the equivalent gate-oxide thickness has to be scaled more aggressively as currently suggested by the ITRS. The suggested scaling scenarios for the equivalent gate-oxide thickness are shown for Fig. 15 Comparison of the TCAD-simulated on-state drain currents in bulk-silicon, single-gate SOI, and double-gate MOSFETs for MOSFET devices scaled as suggested in this work 123 Fig. 16 Comparison of the equivalent oxide thickness in bulk and single-gate SOI MOSFETs according to the ITRS Table 1 (Options B1 and S1) and according to a suggestion of this work (Options B3 and S5) the three transistor architectures considered in Figs. 4, 8, and 12. The transition to a more aggressive gate-oxide scaling suggested here results from the nessecity to compensate the negative impact of the quantum mechanical electron depletion. In Fig. 16, the modified gate-oxide thickness scaling plans (Options B3 and S5) as found in this paper are compared with the initial ITRS specifications presented as Options B1 and S1 for for the bulk-silicon NMOSFETs and the single-gate SOI, respectively. According to the simulations of this work, bulk-silicon MOSFETs need a more aggressive gate-oxide scaling to compensate for a not so good electrostatic control of the electrons in the inversion layer of such MOSFETs. The difference between the ITRS specification and the finding of this work for the gate-oxide scaling becomes larger for smaller gate lengths, but the maximum difference in the effective gate-oxide thicknesses is only about 0.1 nm. This difference seems to be very small, but it is a significant difference for transistor performance. However, when we consider that technologically the required small EOT are implemented using high-k-dielectrics and that the physical thickness of the gate isolation is usually about three to four times larger than EOT, so that also such small differences in EOT can be well controlled technologically. Generally, thin silicon MOSFET architectures, SOI or multi-gate, permit thicker gate oxides as compared to the bulk silicon MOSFET architectures for the same gate lengths. In Fig. 17 a comparison of the DIBL parameter simulated for for different MOSFET architectures is presented. All devices except a double-gate device at 17 nm gate length and single-gate SOI at 18 and 20 nm gate lengths satisfy the condition D I B L < 100 mV/V. The bulk-silicon MOSFETs in the range of gate lengths specied for this architecture in J Comput Electron (2015) 14:192–202 201 5 Conclusion but even more important is it to obtain an enhancement of the on-state drain current at a fixed leakage current with progressing down-scaling. The numerical simulations performed in this work elucidate the role of the most important scaling parameters on transistor performance in the downscaling process. One critical scaling parameter is the equivalent gate-oxide thickness, EOT. Numerical simulations which take the quantum depletion of the electrons near the interface silicon-to-gate-oxide-isolation into account show that a more aggressive scaling of the gate-oxide thickness is necessary to achieve an increase of the on-state current of CMOS FETs with scaling as planned by the ITRS. For single-gate SOI and for double-gate MOSFETs, the silicon body thickness is also a critical parameter. Simulations of this work that include quantum mechanical depletion of the electrons near the silicon surface and effects of elecron scattering on surface roghness and surface phonons show that the silicon thickness scaling as suggested by the 2011 ITRS for high performance MOSFETs is not enough to ensure the necessary suppression of the short channel effects in MOSFETs as planned by ITRS. Thinner silicon layers that amount to about 60 % of the ITRS specification of 2011 are needed to efficiently suppress short channel effects in single-gate SOI and in double-gate MOSFETs. Further, the doping level in the channel is an important factor. According to simulations of this work, a high doping level in the channel is necessary for the bulk-silicon MOSFETs to suppress the short channel effect. In single-gate SOI MOSFETs and in double-gate MOSFETs short-channel effects can be efficiently suppressed by choosing a thin silicon-body thickness. Therefore, low doped or undoped channels are possible for these transitors. The doping level in the channel is not critical for these transistors, provided it is below a limit of about 1 × 1017 cm−3 when doping in the channel does not dominate the electron scattering. The simulations of this work demonstrate that all three MOSFET architectures suggested by the ITRS have a potential to achieve the electrical performance for the gate lengths considered in the ITRS, but the scaling plans for the gate oxide, for silicon body thickness and for the channel doping should be modified to obtain the planned electrical performance of CMOS transistors. The modified scaling scenarios suggested in this work include (a) more aggressive gate-oxide scaling for all three MOSFET device architectures in comparison to the ITRS specifications, (b) lightly doped channels for single-gate thin silicon body SOI MOSFETs and double-gate MOSFETs, (c) thinner silicon bodies for single-gate SOI and double-gate MOSFETs in comparison to the current plans of the ITRS. For the further scaling of CMOS transistors to smaller gate lengths it is important to suppress the short channel effects, Acknowledgments The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under Grant agreement no. 318458 SUPERTHEME. Fig. 17 Comparison of the simulated DIBL coefficients for the bulksilicon, single-gate SOI, and double-gate MOSFETs scaled as suggested in this work Fig. 18 Comparison of the inverse sub-threshold slope for the bulksilicon, single-gate SOI, and double-gate MOSFETs scaled as suggested in this work the ITRS also well satisfy the DIBL reqiurement D I B L < 100 mV /V . The double-gate architecture results in good scaling properties of the DIBL parameters also for extremely short gate lengths down to 6 nm. Figure 18 shows a comparison of the inverse subthreshold slope for the bulk-silicon, single-gate SOI, and doublegate NMOSFETs. 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