Evaluation of a Non-Volatile FPGA based on MRAM technology

Evaluation of a Non-Volatile FPGA based on MRAM technology W.Zhao', E. Belhaire', V. Javerliac2, C. Chappert', B. Dieny2 1. Institut d'Electronique Fondamentale, Universite Paris Sudl CNRS, France 2. SPINTEC, CEA (Commissariat a l 'Energie Atomique) Grenoble/CNRS, France Email: [email protected] Abstract- In this paper, we propose a new structure of FPGA based on MRAM technology; we name it MFPGA (Magnetic FPGA). FPGA based on SRAM technology has been developed in the last years, because of its high speed and near limitless number of reprogramming, however SRAM is volatile thereby the configuration information and the intermediate data will be lost when power is turned off. By using i MTJs (Magnetic Tunnel Junction) as the storage elements of FPGA, Fig 1.1 the position of MTJs we can realize the non-volatility of FPGA, and then we will not need the external memory. In our simulation, the start-up time of circuit In this paper, we will introduce the MFPGA in the second section; can be decreased up to some hundred pico seconds. Except for the the simulation results will be shown in the third section and in the advantage of using MRAM technology is that we will not enlarge the circuit surface, because the storage element MTJs are on the semiconductor surface. dissipation topology will be presented. For our simulation, CMOS 9Onm and 130nm technologies have been used; in the magnetic part, we use the simulation model) [4] of CEA (Commissariat a rapid start-up time, we can also configure the algorithm and logic function of the FPGA circuit very simply and rapidly. The other fourth section the CLB (Configurable logic block) low power l'Energie Atomique), which is based on FIMS (Field induced magnetic switching) [3, 4] writing approach. Index Terms-SRAM, MRAM, non-volatile, high speed, Multi- context, MTJ, FPGA, Magnetic, LUT, Register II.MFPGA J.INTRODUCTION In the last 10 years, FPGA[1] has been developed rapidly, because of its reconfigurability and the ease and low cost of their development process. Although FPGA circuit has a brilliant future, it has the limits of memories. Now FPGA circuit uses SRAM as the intermediate memory; however SRAM is volatile, which means that we have to pre-program all the functions at each power-up and there needs Non-volatile PROM memory outside of the FPGA. This increases the start-up time, the total device cost and the printed circuit board area. (MAGNETIC FPGA) INTRODUCTION In FPGA circuit, there are two types of memory: the configuration memory (LUT and interconnection) and register (Latch or FlipFlop) (Fig 2.1). FPGA Memory Internal Flash [2] technology is now sometimes used to replace the external memory. However it has also some drawbacks, which are the slow reprogramming and the limited number of writing cycles (up to 106), thereby limiting its useful lifetime and it can not be used as the intermediate memory, which will be written very often. Figure 2.1 the two types of memory We introduce them in details and present how they can be realized with MTJs (Magnetic Tunnel Junction) in MFPGA. A. The interconnection memory and the reconfiguration The interconnection memory memorizes the connections between the logic elements. In a conventional FPGA circuit, the structure of g 2a)in s 6 t o nterionnti And 6 SRAM whcsoudbprgamdtteciutsat-. MRAM (Magnetic RAM) [3] is one of the best solutions to bring the non-volatility to FPGA, while keeping a low power dissipation, allowing more than 1012 re-programming times and high writing and reading speed; and having a large retention time up to l0years. By using the magnetic memory cells MTJs (Magnetic Tunnel Junction) [3] in FPGA circuit we can decrease the start-up time of this circuit up to some hundred pico seconds. We can also program the algorithm and logic function of the FPGA circuit simply and rapidly. Moreover, the MRAM writing speed allows us to add a true non-volatility property to all the registers classically used in the FPGA CLB (Configurable logic block)._ r , C MTJs will not take more die area, because they will be on the / semiconductor surface (Fig 1.1) and the dimension of every MTJ is.*> also very small (e.g. 300nmx200nm), thereby the actual layout of semiconductor circuit will not be affected. 1 -4244-0098-8/06/$20.O ©0(2006 IEEE. RIeister onfiguration 1 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:53 from IEEE Xplore. Restrictions apply. tf;s (a) ICICDTO6 re-configuration dead-time. By this way, we can also realize the MFPGA with 2, 3, 4, n configurations. B.Magnetic LUT (Look up table) In FPGA circuit, the structure (Fig 2.4a) of LUT is composed by four elements: a Flash PROM to store the function of the LUT; the inputs, one output and the signal "Enable". The internal structure of the LUT (Fig 2.4b) includes a 16-bit SRAM initialized at startup with the Flash PROM data and a coder to select the memory cell to output. (b) Figure 2.1(a) the structure of interconnection based on SRAM (b) the structure of interconnection based on MRAM outut rt Output In MFPGA, SRAM will be replaced with MRAM (Fig 2.lb), thanks to the non-volatility of MRAM. The MRAM is based on Magnetic Tunnel Junctions (MTJ) [3]. The MTJ behaves as a resistor whose resistance depends on the bit stored in it. As digital levels are required to control the configuration switch a sense amplifier is necessary to convert the resistance variation to digital levels. In the FPGA context this sense amplifier can be simple thanks to the use of two complementary MTJ per bit. This sense amplifier is detailed in section III.A. Inpt=Output LUT nable Inputs coder Enable (a) (b) Fig 2.4 (a) 4-inputs LUT (b) internal structure of 4-inputs LUT For our magnetic LUT, we propose to use a MRAM array to replace both the Flash PROM and the SRAM (Fig 2.5a). By this way, the LUT becomes non-volatile and the external Flash PROM is not needed anymore. write I Output bt uu uu US coder By implementing several MTJ pairs per sense amplifier, multicontext configuration can easily be implemented in the FPGA with a small surface overhead. That way, several algorithms can be predefined in the FPGA to allow a fast dynamical reconfiguration through the use of a signal to select the circuit configuration. This is represented in the Fig 2.2 where a single sense amplifier (SA) is Inputs Enable used for four configurations. For example, let us suppose that, in conventional FPGA, four different algorithms have to be (b ) magnetic LUT (b) the internal implemented like represented in Fig 2.3a. In MFPGA circuit, the '.Fig . 2.5 (a) (a) the structure of 4-input configuration can be controlled by a configuration supervisor structure of MRAM array (Fig2.3b) and the four processing parts will share the same FPGA portion. When So Si="00", data will be processed in the first The MRAM block can be organized as represented in Fig 2.5b algorithm and when aloitman So Sl="O1", will be processed n the h he data wl b roese in j"0"dt o with a sense amplifier (SA) for each memory bit. Alternatively, we second algorithm, etc. MTJ can also use the structure of Fig 2.2 which works as a two inputs LUT and share a single sense amplifier to minimize the chip Iniputs T rMT T W Y T W surface. C. Magnetic Register (Latch or Flip-Flop) 0Ode' 9 Output The CLB is the base logic element of FPGA and it is composed or 8 semi slices. A semi slice includes a LUT and a Register (Fig 2.6 a). The LUT outputs the result of the function; the register saves the result temporarily and synchronizes it with the global clock. The register is usually built with D flip-flop. The conventional structure of a D Flip-Flop includes two elements: Master and Slave, which are both clock-controlled Latch (Figure 2.6 b). The master part is used to write the information in Flip-Flop and the slave part is used to output the information, the global clock and its anti-phase clock control the process. by 4 Figure 2.2 example of 8 MTJs, so 4 pre-defined algorithms it lnput Flb§h PROM serial Alo Alg2 Algo4 (a) (b) |0output (a) (b) Fig 2.6 (a) the basic structure of FPGA (b) Flip-Flop structure Fiue23(a) initialingoih i ovninlFG (b) MFPGA algorithmconfiguration configuration ThisMFPA muti-ontet cnfigraton dastcall reucesthe 1 -4244-0098-8/06/$20.O ©0(2006 IEEE. 2 In this paper, we present the design of a magnetic D Flip-Flop (Fig 2.7), in which a magnetic writing circuit and a sense amplifier replace the master part. This magnetic Flip-Flop can be use to store Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:53 from IEEE Xplore. Restrictions apply. ICICDTO6 B.Magnetic Flip-Flop using Black&Das sense amplifier permanently all the intermediate result and then allow an "instant restart" of the FPGA in case of shutdown (hazardous or not). However, the main disadvantage of this circuit is that the writing circuit uses quite high current to write classically the information in the MTJs and hence requires some large transistors. Nevertheless, alternative solutions to write the MTJs are under investigation and should lead to some improvements of this fact [5]. In tClk With this sense amplifier, we have simulated the three magnetic components and the results on the magnetic Flip-Flop are presented in this paper. In Flip-Flop design, the power-delay product [7] is a good performance evaluator of Flip-Flop, these two parameters are analyzed in the following sections. 1w1_oup 1) Thepropagation time The propagation time includes the writing and reading MTJs time. The writing time is found by the simulation model to be about 580ps. The reading time including the sense amplifier and the Slave circuit is around 200ps. The total propagation time is then around 780ps (Fig 3.3), so the maximum clock frequency of this magnetic register can be estimated to be 1.3GHz with the MFPGA circuit access time of 200ps. _ A IClk . |=Clk Figure2.7 the Master-Slave magnetic Flip-flop III.MFPGA SIMULATION A. Black&Das sense amplifier '_l 1) Introduction All the three magnetic components mentioned above should use sense amplifier; which determines the speed and power dissipation of those logic components. The sense amplifier will have to read the information saved in a small number of MTJs, and so it can follow a simpler scheme than those traditionally adopted in MRAM designs. In this work, a SRAM type sense amplifier proposed by Black and Das[6] is used (see Fig 3. 1). MP1 MP2 ml BLnSen= cl I UT ..,.....II..... > 64-08 put m put 4 U 149n .LI~~~~OT-I QRC, 0 Fig 3.3 the propagation time of this magnetic Flip-Flop MN1 Bitline fasio , th lac elca es The power dissipation of the magnetic Flip-Flop mainly includes the power of the writing circuit and the sense amplifier. In the power analyses, the leakage current is not very significant in l3Onm [8] technology and it is not considered therein. The main power consumption of the sense amplifier occurs during the writing of MTJs with the structure is in equilibration state and a static current passing through it. It depends on the switching frequency, the h Fig 3.1 schema of sense amplifier composed by 5 transistors the Bymprogntramintahei MTsn lacceft candsns complementary inc magnetic~~~~ information by briefly turning on the shorting switch and then By prgraming te MTs o on he lft an therightin rig them t a promptly turning it off. supply voltageT as in Equation (E3.1). p fdd XId (t)dt 2) The reading time If we use all the five transistors in minimum dimension, the reading time is as small as i6ps (Fig 3.2). It can also be decreased by increasing the transistor widths. (E3.1) The power dissipation can be decreased by increasing the resistance of the MTJs (i.e. in parallel magnetic configuration). TOO.72xTox In electrical simulation, a reading time of 1OOps has been obtained q; _e when the width of the PMOS (NMOS) is tOhOnm (585nm, RMTj (E3 .2) -2)Th Teadn thee Thikeso h T are 222.35a no respectively). c es theimlatch cell can sense the m If we t . 0 the aveag energ ofvthesstr barie (2eVfor diesLO h p consumphon sxV2c ense amplQfr occurs of068V thn thReal MJ 6s the6V s+('tr2 e the *pa.igt su e iof theM reading tim is as smal as 160ps (ig 3.2). IVs.n theobiasecvoltage bynraightrnitrits FrmThe equationssi(E3i2)and (e3) theresistance increasesnwithe 000 50 10 15 20 ~~~~~~~~rsit0andcreae the witMTJs sue.inprfalelmasnticonfirmbysiuations. of im 0mpife wihall thee FIg 3.2trcasimulationresult, ths0ene (Figi3.4). transitors wint minmu dimensiOS NMSis15nn(8n, RI=,XO7 X(E2 - a I -424-0098-/06/$2.OO ©006 IEE. 3 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:53 from IEEE Xplore. Restrictions apply. IICDTO 2 2 d *-Magnetic Field Bit line XMlXflT c <_ Magnetic Field Word line .0 Figure 4.1 the writing approach of FIMS < 132 12 1,1 Tox (nm) 13 1,5 Vdd 1 Vdn (a) ON~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-0L t ~ ~ ~ ~ ~ ~ _; ~ ~ ~ ~ ~ ~ ~ ~~~~~~00,100 L]g0 0 6, 4.2 the writing theory schema for magnetic FPGA ~~~~~~~~~~~Figure \ q 0 .1iL]0 S. L]gg V.CONCLUSION - 445 440'33E5 44t'0220 '302SD A We have proposed this new architecture of MFPGA which features simultaneously non-volatility and high speed. By using of the simulation model of MTJ, three magnetic components have been simulated to evaluate the MFPGA performances. The conventional approach to write MRAM leads to an important power dissipation which prevents the replacement of all the classical registers in the FPGA by their non-volatile counterpart. Alternative writing approaches are under investigation. 290'200 '2016' 12T1000 M T J surface (nm'nm) (b) Figure 3.4 (a) Tox; (b) MTJ surface influence the Power dissipation of sense amplifier The simulation model is based on FIMS (Field induced magnetic switching) writing mode. We have mentioned above that the main drawback of this mode is that it implies very high current, some milli-Ampere to write MTJs and leads to highly dissipative writing circuit. Such a circuit is proposed in the Figure 3.5. Its power dissipation is already 35luW for an operating frequency as low as 10MHz. This significant power consumption of FIMS writing mode does not allow replacing all the FPGA registers by their nonvolatile equivalents. Alternative writing approaches, like TAS (Thermal assisted switching) [9] or Spin transfer[1O], are under consideration in our laboratory. VI.ACKNOWLEDGMENT The work and results reported were obtained with research funding from the European Community under the sixth Framework, Contract Number 510993: MAGLOG. The views expressed are solely those of the authors, and the other Contractors and/or the European Community cannot be held liable for any use that may be made of the information contained herein. VWC REFERENCES (1) K.Abe, T.Omori, M.Naraoka "A Programmable Logic Array Suitable for Use Input 01~>- in EN International Volume, Issue, 13-15 Dec. 2004 pp: 903 - 906 (4) V. Javerliac et al, "Magnetic tunnel junction compact device model for electrical simulations of spintronic components", Magnetism and Magnetic Materials 2005, Oct. 30 - Nov. 3, San Jose, California (5) W.C.Jeong Highly scalable MRAM using field assisted current induced switching Symposium on VLSI Technology Digest of Technical Papers. , N Digital System Design Laboratories", IEEE Trans. on Education, Vol. 35, no. 4, Nov. 1992. (2) Kevin Morris, "Flash News Flash", FPGA and Programmable Logic Journal. January 25, 2005. Stuart S.P.Parkin, "Spintronic Materials and Devices: Past, Present and (3) future" Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE NOR Figure 3.5: the writing circuit of bitline (6) IV.THE WRITING TOPOLOGY OF MAGNETIC FPGA (7) In the writing approach of FIMS mode; there are classically two writing currents: the bit line and the word line (Fig 4.1). When W. C. Black Jr. and B. Das "Programmable logic using giant-magneto- resistance and spin-dependent tunneling devices" J. Appl. Phys., Vol. 87, No. 9, 1 May 2000 pp: 6674 -6679 V.Stojanovic et al, "Comparative analysis of master-slave Latches and Flip- Flops for high-performance and low-power systems" IEEE Journal of solid- state circuits, Vol. 34, NO.4, April, 1999 adapted to a magnetic FPGA design, the word line can pass above ' . all the MTJs of a semi-slice (one LUT and one register) (8) Nam Sung Kim et al, "leakage current: Moore's law meets the static power" computer society November 2003, pp 68 -74 ~~~~~~~~~IEEE (9) J.-P.Nozieres et al, ";Memoire magnetique a consummation reduite" FR Patent semi-slices in one CLB (vertically in the Fig. 4.2). As a FPGA (10) A. Fert et al, "Magnetization reversal by injection and transfer of spin: (horizontally in the Fig 4.2), and the bit line is shared among some 0112123 experiments and theory" Journal-of-Magnetism-and-Magnetic-Materials. 2004; 272-276 pt. 3: 1706-11 configuration is usually completely reloaded in the CLB, this architecture helps to decrease the power dissipation per MTJ as it allows a single current to write several MTJs in parallel. 1 -4244-0098-8/06/$20.O ©0(2006 IEEE. View publication stats Authorized 4 licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:53 from IEEE Xplore. Restrictions apply. ICICDTO6 May