Uper

Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R Research Scholar, Department of ECE, Karpagam Academy of Higher Education, Coimbatore [email protected] Dr.Manimegalai, P Professor, Department of ECE, Karpagam Academy of Higher Education, Coimbatore [email protected] Dr.Kamalraj, S Associate Professor, Department of ECE, Karpagam Academy of Higher Education, Coimbatore [email protected] Abstract: The EEG signal extraction offers an opportunity to improve quality of life in patients, which has lost to control the ability to control their body, with impairment of locomotion. Electroencephalogram (EEG) signal is an important information source for underlying brain processes. The signal extraction and denoising technique obtained through time-domain, adaptive line enhancer (ALE) extracts the signal coefficient, and classifies the EEG signals based on FF network. The adaptive line enhancer is used to update the coefficient during the runtime with the help of adaptive algorithms (LMS, RLS, Kalman Filter). In this work the least mean square algorithm was employed to obtain the coefficient update with respect to the corresponding input signal. Finally, use Matlab 7.0 and verilog HDL language are used to simulate the signals and get classification accuracy rate was 80%. Experiments show that this method can get high and accurate rate of classification. In this paper, it is proposed that a low-cost use of field programmable gate arrays (FPGAs) can be used to process EEG signals for extracting and denoising. As a preliminary study, this work shows the implementation of a Neural Network, integrated with ALE for EEG signal processing. The preliminary tests with the proposed architecture for the activation function proved to be feasible both in terms of the requirement precision as well in processing speed. Keywords: Extraction. EEG, FFNN, ALE, Perspectivas em Ciencia da Informacao, v.22, sp.5, p37. , Nov./ Dec. 2017 FPGA, Denoising, ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; 1 Introduction People around the round suffer from a disease that inhibits and restrict their movements, confining them to a wheelchair or on a bed for the rest of their lives. Nowadays, due to the improvement of technology, people have a deep understanding of brain function and diseases and have taken measures to prevent that which facilitates the patient's autonomy and consequently improves the quality of life. Brain signals, does not rely on the normal brain output pathways (i.e. peripheral nerve and muscle). During the process of thinking that happens in the brain, the EEG signals monitor and analyse, understand the intention of the people and pass on the information to the brain directly about the outside world and it can realize more forms of applications. As long as the brain is able to normally understand in theory through a brain signal analysis the ALE technique is used to obtain the brain stem damage or paraplegia complete closure patients that have a very broad practical prospect [1-3]. EEG signal analysis, the signal extraction and denoising for the earlier stage treatment and rehabilitation for neurological disorders in the fields is considered as an important research method [4-5]. Artificial Neural Networks have been widely used in many fields. A great variety of problems can be solved with ANNs in the areas of pattern recognition, signal processing, control systems etc. Most of the work done in this field until now consists of software simulations, investigating capabilities of ANN models or new algorithms. But hardware implementations are also essential for applicability and for taking the advantage of neural network’s inherent parallelism. There are analog, digital and also mixed system architectures proposed for the implementation of ANNs. The analog system architectures are more precise but it is difficult to implement and have problems of weight storage. In Digital designs the advantage of low noise sensitivity, and weight storage does not arise due to the advance in programmable logic device technologies, FPGAs has gained much interest in digital system design. They are user configurable and there are powerful tools for design entry, syntheses and programming and the fundamental block diagram of biomedical signal processing are shown in figure 2. Before beginning a hardware implementation of an ANN, a number of format (fixed, floating point etc.) must be considered for the inputs, weights and activation function. And also the precision (number of bits) should also be considered. Increasing the precision of the design elements significantly increases the resources used. Accuracy has a great impact in the learning phase, so the precision of the numbers must be as high as possible during training. However during the propagation phase, lower precisions are acceptable [6]. The resulting errors will be small enough to be neglected especially in classification applications [7-9]. Perspectivas em Ciencia da Informacao, v.22, sp.5, p38. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; 2 Artificial Neural Network (ANN) An Artificial Neuron (AN) is a model of biological neuron. Where each AN receives signals from the environment or other ANs, gathers these signals applying some activation function to the signals sum and when fired transmits signal to all connected ANs. Input signals are inhibited or excited through positive or negative numerical weights associated with each connection to AN the firing of the AN and the strength of the exciting signal are controlled via a function referred to as activation function. The AN collects all incoming signals and computes a net input signal asa function of the respective weights. The net input serves to the activation function which calculated the output signal of the AN. An ANN is a layered network of ANs. ANN may consist of input, hidden and output layers. ANs in one layer are connected fully or partially to the ANs in the next layer [10], as shown in Figure (1) Input Layers Hidden Layers Output Layer Figure 1 Block Diagram of a Single Neuron The choice to build a neural network in digital hardware comes from several advantages that are typical for digital systems. Digital designs have the advantage of low noise sensitivity, and weight storage is not a problem. With the advance in programmable logic device technologies, FPGAs has gained much interest in digital system design [11]. Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. [12]. FPGA are an excellent technology for implementing NNs hardware. Executing a NN on FPGA is a relatively easy process. For lessening the design circuitry the training will be done independently off line the FPGA, once the training is completed and the correct network weights is obtained these weights will be hard implied on FPGA. The accuracy in which these weights can be coded will depends upon the number of bits existing to implement the weights. Parallelism and dynamic adaption are two computational characteristics typically related with ANN FPGA-based reconfigurable computing architecture are well suited to implement ANNs as one can develop concurrency and rapidly reconfigure to adapt the weights and topologies of an ANN [13]. Perspectivas em Ciencia da Informacao, v.22, sp.5, p39. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; 3 Denoising and Separation System Denoising the EEG signal is also considered as a vital task to be performed before classification. The authors of [14] combined two methods namely, Empirical Mode Decomposition (EMD) and Higher Order Statistics (HOS) for effective signal denoising. The noisy signals were detected by Gaussianity estimators and removed. The maximum suppression of signal noise was performed with thresholding techniques. In [15], the authors performed a comparative analysis on the performance of STFT, Wavelet Transform (WT), Least Mean Square (LMS) and Recursive Least Square (RLS) in the aspect of denoising and concluded the paper with the statement that adaptive algorithms are the best in denoising the signal. EEG signal preprocessing performed with wavelet transformation has been described in [16]. Physiological System (Patient) Signal Data Acquisition Filtering to Remove Artifacts Detection of Events And Components Device Output Stimulus Generation Figure 2 Block Diagram of Signal Processing The implementation of signal separation and denoising system proposed in [17], aims at processing of biological signals, more specifically, the classification and processing of EEG signals using artificial neural networks (ANNs) integrated with Adaptive Line Enhancer (ALE). Both the techniques are employed to obtain the minimum area occupied and processing speed that are critical and the architecture is shown in figure 4. The use of field-programmable gate array (FPGA) devices has been gradually replacing the Digital Signal Processors (DSPs), mainly due to the great power of parallel processing, large capacity and cost competitiveness, that new FPGAs have [18]. The literature shows that the implementation of ANNs in FPGAs devices is feasible and it has an advantage [19], both in terms of capacity and cost. 4 Proposed Technique The proposed signal extraction and denoising technique represented in figure.3, processes data used from the obtained real time data or a stored one. The ANN algorithms implemented in MATLAB gives a mean accuracy of 84.3 % for the classification of the EEG signal between the left and right hand classes. The implementation of the Neural Network block is marked in figure 3 on an FPGA device. The architecture used in its implementation and the results obtained are discussed in the flowing sections. The literature proposes the use of data with 8-bit floating point, as in [20]. However, this approach has as main drawback of imprecision of the results, which carries a high number of false positives ones [2122]. Perspectivas em Ciencia da Informacao, v.22, sp.5, p40. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Clock Address Weight Rom Clock Input Load Output Multiplier Accumulator Enable Out Enable Figure 3 VLSI Implementation of ANN To overcome this problem, this paper proposes the use of floating point representation with 32 bit width of precision, aiming at a more accurate comparison between the expected results and those obtained through simulations with MATLAB. In order to find the balance between speed and area used, the hardware implementation of the artificial neural network is being done with the help of Verilog HDL language. All the circuit elements work in 32-bit single precision floating point, then it is possible to obtain greater precision. However, this precision is obtained at the cost of increases in area occupied by each component, as well the total processing time. But the FPGA used can easily deal with this type of request and further permits greater flexibility in some network points. The neural network has then been trained with those features to get the appropriate results. Moreover, the authors have claimed that further research could be carried with classifiers having high potential to compute the detection methodology. X(n) +  E(n) +  E'(n) -  D(n) Adaptive Filter W(n) Y(n) Adaptive Algorithm Non Linear ANNs Adaptive Filter Y'(n) E'(n) Figure 4 Architecture for Integration of ANN with ALE 5 Results Diagnosing epilepsy is a tedious task requiring observation of the patient. Through an EEG, gathering of additional clinical information becomes a difficult task. An artificial neural network that classifies subjects as having or not having an epileptic seizure provides a valuable diagnostic decision support tool for neurologists treating potential epilepsy, since differing etiologies of seizures result in different treatments. Perspectivas em Ciencia da Informacao, v.22, sp.5, p41. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Figure 5 Simulated Wave Form of ANN-ALE Figure 6 RTL Design of Proposed Architecture for ANN–ALE The simulated output waveform was obtained in Xilinx 10.1. in this waveform the input signal are converted in IEEE 754 signal precession 32 bit format to feed the input signal and the corresponding output signal was obtained in 32 bit and its verified the SNR and MSE in Digital format are shown in figure 5. In Figure 6 shows the HDL to RTL view of the proposed architecture of ANN – ALE was obtained in cadence Encounter TMSC 90nm technology. Figure 7 Utilization of Gates and Area (µm) in ANN-ALE Figure 8 Utilization of Power (nW) in ANN-ALE Perspectivas em Ciencia da Informacao, v.22, sp.5, p42. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Figure 9 Utilization of Time (pS) in ANN-ALE In table 1 contains the utilization of gates like sequentionl, logical and inverters to utilized the architecture of ANN – ALE and the corresponding area utilized in each circuits and the graphical representation are shown in figure 7. Fron table 2 contains the power (leakage, dynamic) and time (delay and arrival) utilizing the proposed architecture and the graphical representation are shown in figure 8 and figure 9. Table 1 Utilization of gates and area Utilization Type sequential logic inverter Total of Gates Gates 654 11745 1250 13649 and Area Area(µm) 16223 106213 2838 125274 Table 2 Utilization of power and time in ANN-ALE Utilization of Power (nW) Utilization of Time (pS) Leakage 2507 Delay 4980 Dynamic 4544016 Arrival 12363 Total 4546523 Total 17343 Perspectivas em Ciencia da Informacao, v.22, sp.5, p43. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Table 3 Error Comparison of various filter orders obtained in ANN–ALE Table 3 shows the error comparison of various adaptive filter order such that N = 2,4,8 and 16 integrated with the nonlinear feed forward conventional neural network system. The neural network system trained through trainlm feed forward algorithm to train the entire network to obtain the SNR. 6 Conclusion This work shows the implementation of a Neural Network integrated with ALE for EEG signal process. The adaptive line enhancer enhances and acquires the excepted output from the input signal with the assistance of adaptive algorithm. The preliminary tests with the proposed architecture for the SNR, MSE, activation function, proved to be feasible both in terms of the requirement precision as well in processing speed. However, tests Perspectivas em Ciencia da Informacao, v.22, sp.5, p44. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; and changes must be done on the network and ALE, so that the optimum point between area occupied, precision and speed can be reached. The proposed system was obtained the area 125274 µm and the power requirement 4546523 nW is obtained in TMSC 90nm cadence environment. As a future work we tend to implement all the neural networks that pre-processes the EEG signals, so as to check the obtained ends up in each approaches, both software system and hardware. R.Suresh Kumar has completed his B.E. Electronics and Communication Engineering in the year 2004 from Thanthai Periyar Government Institute of Technology, Vellore. He received his M.E. degree (Applied Electronics) in the year 2007 from PSG College of Technology, Coimbatore. Currently he is doing his research at Karpagam Academy of Higher Education, Coimbatore. His areas of interest are VLSI and signal processing. Dr.P.Manimegalai has completed her B.E. Biomedical Instrumentation Engineering in the year 2000 from Avinashilingam University. She obtained her M.E Applied Electronics from Govt. College of Technology by 2008. She obtained her Ph.D. from Anna University, Chennai from 2013. Currently she is working as Professor in ECE Department at Karpagam Academy of Higher Education, Coimbatore. Her areas of interest are Biosignal processing and image processing. She has published more than 20 national and international journals. Dr. Kamalraj Subramaniam received his Ph.D. degree in Mechatronic Engineering 1 from University Malaysia Perlis, Perlis, Malaysia in 2014. Currently, he is an Associate Professor, Dept of ECE, Karpagam Academy of Higher Education, Coimbatore, India. His research interests include biomedical signal processing, artificial neural networks. References Melody, M. M. 2003. Real-World Applications for Brain-Computer Interface Technology. IEEE Transactions On Neural Systems Rehabilitation Engineering, 11(2) (2003), 162-165. Schalk, G., McFarland, D. J., & Hinterberger, T. 2004. BCI2000: A GeneralPurpose Brain-Computer Interface (BCI) System. IEEE Transactions On Biomedical Engineering, 51(6) (2004), 1034-1043. Leeb, R., & Pfurtscheller, G. 2004. Walking through a Virtual City by Thought. Proceedings of the 26th Annual International Conference of the IEEE EMBS (pp. 1-5), 2004. Perspectivas em Ciencia da Informacao, v.22, sp.5, p45. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Nojima, K., & Ogawa, S. 1987. Measurement of surge current and voltage waveforms using optical-transmission techniques. IEEE Proceedings, 134(6) (1987), 415-422. Fujita, S., Hosokawa, N., & Shibuya, Y. 1998. Experimental investigation of high frequency voltage oscillations in transformer winding. IEEE Trans on Power Delivery, 13(4) (1998), 1201-1207. Stevenson, M., Weinter, R., & Widow, B. 1990. Sensitivity of Feedforward Neural Networks to Weight Errors. IEEE Transactions on Neural Networks, 1(2) (1990), 71-80. Blake, J. J., Maguire, L. P., McGinnity, T. M., Roche, B., & McDaid, L. J. 1998. The Implementation of Fuzzy Systems, Neural Networks using FPGAs. Information Sciences, 112 (1998), 151-168. Cox, C., & Blanz, W. 1992. GANGLION-A Fast Field-Programmable Gate Array Implementation of a Connectionist Classifier. IEEE Journal of Solid-State Circuits, 27(3) (1992), 288-299. Krips, M., Lammert, T., & Kummert, A. 2002. FPGA Implementation of a Neural Network for a Real-Time Hand Tracking System. Proceedings of the first IEEE International Workshop on Electronic Design, Test and Applications, 2002. Akkar, Dr. H. A. R., & Mahdi, F. R. 2010. Implementation of Digital Circuits Using Neuro-Swarm Based on FPGA. International Journal of Advancements in Computing Technology, 2(2) (2010). Ali, H. K., & Mohammed, E. Z. 2010. Design Artificial Neural Network Using FPGA. International Journal of Computer Science and Network Security, 10(8) (2010). Guccione, S. A., & Gonzalez, M. J. 1994. A neural network implementation using reconfigurable architectures. More FPGAs, Abington, Oxford, UK, 1994, 443-451. Muthuramalingam, A., Himavathi, S., & Srinivasan, E. 2008. Neural Network Implementation Using FPGA: Issues and Application. International Journal of Information Technology, 4(2) (2008), 86-92. Tsolis, G., & Xenos, T. D. 2011. Signal Denoising Using Empirical Mode Decomposition and Higher Order Statistics. International Journal of Signal Processing, Image Processing and Pattern Recognition, 42 (2011), 91-106. Alam, M., Islam, M. I., & Amin, M. R. 2011. Performance Comparison of STFT, WT, LMS and RLS Adaptive Algorithms in Denoising of Speech Signal. IACSIT International Journal of Engineering and Technology, 3(3) (2011), 235-238. Perspectivas em Ciencia da Informacao, v.22, sp.5, p46. , Nov./ Dec. 2017 ISSN: 1413-9936 Implementation of neural network with ALE for EEG signal processing Suresh Kumar, R.,et,al; Chavan, A. S., & Kolte, M. 2011. EEG Signal Preprocessing using Wavelet Transform. International Journal of Electronics Engineering, 3(1) (2011), 510. Braga, R. B. 2011. Processamento de Sinais de EEG para uma Interface Cérebro-Computador. Technical Report. UCPel, Pelotas, 2011. An Independent Analysis: The Evolving Role of FPGAs in DSP Applications, 2007, BDTI (www.BDTI.com). Krips, M., Lammert, T., & Kummert, A. 2002. FPGA Implementation of a Neural Network for a Real- Time Hand Tracking System. Proceedings of the first IEEE International Workshop on Electronic Design, Test and Applications, 2002. Sahin, S., Becerikli, Y., & Yazici, S. 2006. Neural Network Implementation in Hardware Using FPGAs. Lecture Notes in Computer Science, 2006, NUMB 4234, 1105-1112 Omondi, A. R., & Rajapakse, J. C. 2006. FPGA Implementations of Neural Networks, (Eds.) 2006, XII, Ed. Springer. Ossoinig, H., Reisinger, E., & Steger, C., Weiss, R. 1996. Design and FPGAImplementation of a Neural Network. Proceedings of the 7th International Conference on Signal Processing Applications & Technology (pp. 939-943), 1996. Perspectivas em Ciencia da Informacao, v.22, sp.5, p47. , Nov./ Dec. 2017 ISSN: 1413-9936