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1989, [1989] Proceedings of the 1st European Test Conference
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7 pages
1 file
This work presents two new methods for the calculation of node signal probabilities in combinational networks that improve the state of the art by providing a better accuracy than existing algorithms and a deeper insight in the effects of first order correlations due to multiple fan-out reconvergencies. The proposed algorithms are shown to favorable compare with existing procedures in the analysis of significant benchmarks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
We analyze the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classillcation of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type Wig determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows us to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits indicate that the methods are applicable for fast estimation of gate signal probabilities in general circuits. Flnally, this work provides a complete generalization of earlier work on relating aggregate structural characteristics of a circuit to its signal probability behavior.
IEEE Transactions on Computers, 2000
The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. Given the probability of faults occurring in the circuit and the probabilities of the input combinations, it is possible to determine the likelihood of the output being correct. The signal reliability of the output is thus defined as the probability that the circuit output is correct. The first method evaluates the contribution of each fault to the reliability of the circuit and requires the enumeration of the behavior of each fault in the entire fault set. The use of McCluskey and Clegg's characterization of faulty networks by evaluating the functional equivalence classes of the network is a way to reduce the amount of computation involved. Lower bounds can be obtained by considering a restricted fault set, for example, the single fault set. The second method uses a probabilistic model of logical circuits and consists of straightforward operations which can easily be automated. The method also yields the signal reliability and has the capability of very easily specifying the individual fault probabilities of all the circuit lines independently.
Microelectronics Reliability, 2010
Probabilistic reliability analysis is a common approach in logic circuit reliability analysis. Existing methods suffer from accuracy or scalability problems for large circuits because of combinatorial explosion. In this work we show how the use of conditional probabilities can overcome scalability problems while maintaining accurate reliability estimation. The source of accuracy and scalability problems in these approaches is the presence of reconverging signals. An efficient use of conditional probabilities used to decorrelate signals allows for fast and accurate reliability analysis.
Proceedings of the …, 2004
Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increasingly important in combinational logic circuits. Combinational logic is resilient to soft errors due to three masking phenomena: (1) Logical Masking, (2) Electrical Masking, and (3) Latching-window Masking. This paper concentrates on logical masking, and proposes a probabilistic model which calculates the Soft Error Rate (SER) of any output node in combinational logic circuits, based on inherent logical masking properties. Approach observed in Literature Soft-Error Transient (SET) can occur at ANY Input Node! Proposed Model
IEEE Transactions on Computers, 2000
Redundant systems are designed using multiple copies of the same resource (e.g., a logic network or a software module) in order to increase system dependability. Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations of the same logic function. In a recent paper, we presented a metric to quantify diversity among several designs. The problem of calculating the diversity metric is NP-complete (i.e., can be of exponential complexity). In this paper, we present efficient techniques to estimate the value of the design diversity metric. For datapath designs, we have formulated very fast techniques to calculate the value of the metric by taking advantage of the regularity in the datapath structures. For general combinational logic circuits, we present an adaptive Monte-Carlo simulation technique for estimating accurate bounds on the value of the metric.
VLSI Design, 2001
Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem assuming real gate delay model is reduced to the zero delay switching activity evaluation problem at specific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time parameter is introduced. Moreover, a mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero delay based parameters is presented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) is also presented. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.
ACM Transactions on Design Automation of Electronic Systems, 2008
We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate_variables and eliminate_redundant_variables , which aid in the numerical computation of circuit PTMs. W...
IEEE Transactions on Computers, 1978
Metal-oxide-semiconductor (MOS) logic elements offer advantages over bipolar logic elements, such as smaller size, complexity, and power consumption, as well as more flexibility and versatility. Since MOS is playing a major role in large-scale integration (ISI), synthesis ofMOS networks with a large number of variables is very important. In this paper, an efficient algorithm for computer-aided synthesis of MOS combinational logic networks is presented. The algorithm can synthesize both completely and incompletely specified switching functions ofa large number ofvariables. It rapidly generates an easily testable MOS network with a near-minimum number of MOS complex cells and field-effect transistors (FET's). A 10-variable example is given to illustrate the algorithm step-by-step. The algorithm has been programmed in Fortran IV for SPERRY UNIVAC 1108. Many randomly generated switching functions of various numbers of variables have been executed by the computer and the required amounts of computing time and memory space are reported.
IEEE Transactions on Computers, 1973
In this paper, we are concerned with the problem of generating minimal fault-detection experiments for fanout-free combinational logic networks. We establish the greatest lower bound on the necessary number of fault-detecting tests and show in a systematic way how such experiments can be obtained.
2007
ABSTRACT. The combinational logic circuit (CLC) is an important chapter in the project activity of the electronic equipments. If the number of variables is greater than three the project activity with Veitch-Karnaugh diagrams become very difficult. On the other side, the feedforward artificial neural networks have several characteristics like noise immunity, fault tolerance etc. that can be advantages for logical circuits made by these networks. In this papers we presents a new method in simulation of the combinational logic circuit with the neuronal network. There are two important advantages that we can remark: the number of transistors is reduced and the design will become simpler.
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