11 GHz CMOS frequency synthesiser

11 GHz CMOS SD frequency synthesiser V.A. Solomko and P. Weger A fully integrated 11 GHz fractional-N PLL with a three-stage MASH SD modulator with DC dither in all stages is implemented in a standard 0.13 mm CMOS technology. The synthesiser generates no fractional spurs at frequency offsets outside the loop bandwidth and a small number of fractional spurs with the power not exceeding
44 dBc within the loop bandwidth at the carrier frequency of 11 GHz. Introduction: A fractional division technique used in frequency synthesisers allows obtaining fine frequency resolution and fast switching speed while possessing low phase noise level and reference frequency feedthrough suppression. In spite of the good phase noise suppression in fractional-N frequency synthesisers, complete elimination of fractional spurs from the output signal still remains a challenge. A digital SD modulator together with a programmable divider implements the fractional division technique in frequency synthesisers. The spectral purity of a synthesiser’s output signal depends on the SD modulator architecture and how it selects the instantaneous division ratio. A multiple stage digital SD modulator architecture (referred as a MASH) became a widely used solution for PLL applications since it allows building a stable device independently of its order which can be easily implemented in the integrated circuits [1]. One drawback of the digital MASH SD modulators considered in this Letter is their tendency to generate limit cycles with a short repetition period when a constant digital signal with zero least significant bits (LSB) is applied to the modulators. This disadvantage is especially significant for frequency synthesis applications since it can cause spurious signal generation at the output of the PLL. Dithering technique: A technique called ‘dithering’ is used to eliminate or reduce periodicity of the modulator’s output signal and thus compensate fractional spurs. A widespread dithering implementation in digital MASH modulators is setting the LSB of the input word into active level [1]. The density and power of fractional spurs in such a case is proportional to the capacity and order of the modulator’s compound stages. Significant capacity extension allows compensation of considerably fractional spurs, but leads to an increase of the modulator’s complexity and size. CLK CLK 3 differentiator overflow overflow CLK overflow 12 bit accumulator 10 bit accumulator A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> 2 C1<1> C1<0> CLK 1 – input buffer 2 – current reference 3 – CP and PFD 4 – loop filter 5 – VCO 6 – CML logic 7 – prescaler 8 – SD modulator 9 – III-wire bus register 10 – pad driver 5 C2<1> C2<0> dithering bits CLK 4 76 3 8 10 1 2 PLL 9 Fig. 2 Die photograph of synthesiser Experimental results: The 11 GHz CMOS fractional-N PLL with the MASH SD modulator described in the preceding Section (Fig. 1) was fabricated in a standard 0.13 mm CMOS technology. The die photograph is shown in Fig. 2. When no dithering is applied to the second and third stages the best-case spurious will be at frequency offsets of n  ( fref=2=2k1) apart from the carrier, where fref ¼ 64 MHz is the clock frequency of the modulator, k1 ¼ 10 is the capacity of the first accumulator, n is an integer number. The measured phase noise= spurious diagram for this case is shown in Fig. 3. The LSB of the input word A<9:0> switched to logical ‘1’ level ensures that the bestcase spurious performance is observed, giving spurious tones at frequency offsets of n  31.25 kHz. phase noise, dBc/Hz; spurious level, dBc 3 blocks numeration: compensation network differentiator 14 bit accumulator Y stages, while keeping dependence of spurious signals distribution only on the last stage. 2. Since constant logical ‘1’ level is used as a dither, no additional circuit for dithering signal generation is required. The two advantages mentioned above lead to decrease in modulator size and complexity and minimisation of its influence on the analogue part in the case of a fully integrated synthesiser. In spite of the improved periodicity of limit cycles, the described modulator still generates spurious tones since there is no randomness in the proposed device. carrier 10.792074065 GHz –30 –37 –44 –51 –16.8528 dBm –58 –65 –72 –79 –86 –93 –100 –107 –114 –121 –128 –135 –142 103 A<9:0> = 0101000001 C1<1:0> = 00 C2<1:0> = 00 104 105 106 107 frequency offset, Hz Fig. 1 Implemented SD modulator block diagram Fig. 3 Phase noise diagram with constant dithering in first stage A 10-bit input digital MASH 1-1-1 (three stages of first order each) modulator with a DC dither in the second and third stages (see Fig. 1) is presented in this Letter. Additional bits to the second and third accumulators are added (C1<1:0>, and C2<1:0>) to which logical ‘1’ level is applied. Such dithering topology was already used in SD ADCs [2], but to the authors’ knowledge has not yet appeared in the literature as applied to fractional-N PLLs. The merits of the implemented structure are as follows. 1. It allows the reduction of the capacity of the first and second After adding the dithering signal to the subsequent accumulators spurs move to the lower frequency offsets and their power decreases, yielding the spurious at frequency offsets n  (fref=2k3), where k3 ¼ 14 is the number of bits in the third stage of the MASH modulator. The measured phase noise=spurious plot with a dithered modulator is presented in Fig. 4. The fractional spurs are observed at frequency offsets of n  3.9 kHz and their power does not exceed
44 dBc level. Some of ELECTRONICS LETTERS 12th October 2006 Vol. 42 No. 21 phase noise, dBc/Hz; spurious level, dBc the observed spurious tones (at frequencies 38.8, 58.5, 200 kHz) common for both phase noise diagrams are caused by the external factors: the second is generated by the reference crystal oscillator, and the 200 kHz spur is probably introduced by the power supply cables, since 200 kHz is a common switching power supply frequency. The overall synthesiser performance summary is presented in Table 1. carrier 10.792073698 GHz –30 –37 –44 –51 –16.8590 dBm –58 –65 –72 –79 –86 –121 –128 –135 # The Institution of Engineering and Technology 2006 14 August 2006 Electronics Letters online no: 20062536 doi: 10.1049/el:20062536 V.A. Solomko and P. Weger (Chair of Circuit Design, Brandenburg University of Technology Cottbus, Erich-Weinert-Str. 1, D-03046 Cottbus, Germany) E-mail: [email protected] –93 –100 –107 –114 Conclusion: A fully integrated 11 GHz fractional-N PLL with a MASH SD modulator with dithering in all stages is demonstrated. The designed multistage SD modulator consumes 14% more current (1.059 against 0.91 mA at 64 MHz reference frequency) and occupies 13% additional area compared to the conventional MASH 1-1-1 modulator without dithering. References 1 Miller, B., and Conley, R.J.: ‘A multiple modulator fractional divider’, IEEE Trans. Instrum. Meas., 1991, 40, (3), pp. 578–583 2 Norsworthy, S.R., Schreier, R., and Temes, G.C.: ‘Delta-sigma data converters: theory, design, and simulation’ (IEEE Press, New York, 1997, 1st edn.) A<9:0> = 0101000001 C1<1:0> = 11 C2<1:0> = 11 –142 103 104 105 106 107 frequency offset, Hz Fig. 4 Phase noise diagram with constant dithering in all stages Table 1: 11 GHz frequency synthesiser performance summary Technology 0.13 mm CMOS Supply voltage 1.5 V Current consumption 63 mA PLL size 800  800 mm Reference frequency Output frequency range 64 MHz PLL capture range Frequency resolution Phase noise 10.24–12.55 GHz (18%) VCO tuning range 10.6–11.6 GHz (9.1%) 18 kHz In-band phase noise <
80 dBc=Hz Noise floor
140 dBc=Hz Reference spurs
52 dBc Fractional spurs
44 dBc Maximum lock time 8 ms ELECTRONICS LETTERS 12th October 2006 Vol. 42 No. 21