NBTI stress on power VDMOS transistors under low magnetic field

IEEE Transactions on Device and Materials Reliability, 2017

 Abstract-In this paper, we report an experimental evidence of the impact of applied a low magnetic field (B<10mT) during negative bias temperature instability (NBTI) stress and recovery, on commercial power double diffused MOS transistor (VDMOSFET). We show that both interface (ΔN it) and oxide trap (ΔN ot) induced by NBTI stress are reduced by applying the magnetic field. This reducing is more pronounced as the magnetic field is high. However, the dynamic of interface trap during stress and recovery phase is not affected by the applied magnetic field. While, the dynamic of oxide trap is affected in both stress and recovery phases.

Micro Electronic and Mechanical Systems, 2009

Microelectronics Reliability, 2018

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxidesemiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

Solid-State Electronics, 2013

Combining simultaneously on the fly interface-trap (OTFIT) and the reverse voltage variation of source and drain (S/D) during measurement phase of measure/stress/measure (MSM) sequences, we have been able to scan the negative bias temperature instability (NBTI) across the channel length of PMOS transistors. In addition, we have analyzed the generation and evolution of interface-trap distribution with respect to the transistor gate length. We have found that NBTI-induced interface-trap density, DN it are not uniform along the channel. The experimental results reveal an evident propagation of the NBTI degradation. This propagation starts from S/D channel edges and penetrates into the channel center. It is accelerated by temperature and electric field until saturation. However, field-accelerated propagation seems more important than temperature-accelerated one. Further, transistors with shorter channel length degrade more rapidly than those with longer channel length. We have also shown that the channel length has a great effect on NBTI features such as the apparent activation energy and time power-law exponent. These results suggest that diffusion-limited process is not the sole source of the time degradation dependence, but also gate length have to be taken into account.

As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, reliability concerns mainly Negative Bias Temperature Instability (NBTI) becomes a major challenge. NBTI degrades the performance of a PMOS transistor under a negative gate stress. The after effects of NBTI include: (a) threshold voltage increase of PMOS transistor, (b) drain current degradation, and (c) speed degradation. Elevated temperature and the negative gate stress play an important role in degradation of Gate Oxide which further degrades the above said parameters. Before any circuit design Stress Analysis becomes important for any device in order to get the complete performance of the circuit. Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper basically we have analysed the effect of temperature variations on NBTI for a buffer.

Microelectronics Reliability, 2005

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found

Negative Bias Temperature Instability(NBTI) has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, stress analysis or reliability concerns mainly Negative Bias Temperature Instability (NBTI) becomes a major challenge. Stress Analysis becomes important for any digital circuit as it predicts the life time of the circuit in terms of the degradation of device parameters. NBTI degrades the performance of a PMOS transistor under a negative gate stress. The after effects of NBTI include: (a) threshold voltage increase of PMOS transistor, (b) drain current degradation, and (c) speed degradation. Elevated temperature and the negative gate stress play an important role in degradation of Gate Oxide. Before any circuit design Stress Analysis becomes important for any device in order to get the complete performance of the circuit. Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper basically we have studied the Stress Analysis and the impact of temperature of NBTI on a CMOS inverter circuit.

Journal of Applied Physics, 1977

One of the most important degradation effects observed in MNOS memory transistors is a negative shift of the threshold window. This negative shift is caused by a strong increase of the density of Si-SiO, surface traps. This effect has been proposed to be caused by the same effect that is observed in MOS devices subjected to negative-bias stress (NBS). In this paper, a detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (2S-12S'C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented. Two different behaviors are observed. At low fields the surface-trap density increases as t 114 and at high fields it increases linearly with the stress time t. The low-field behavior is temperature and field dependent and the zero-field activation energy is determined to be 0.3 eV. The high-field behavior is strongly field dependent but independent of temperature. A physical model is proposed to explain the surface-trap growth as being diffusion copt rolled at low fields and tunneling limited at high fields. A comparison with MNOS degradation is made and it was found to be related to the t 1.'4 behavior mentioned above.

Microelectronics Reliability, 2007

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N À channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO 2 /Si barrier.

Solid-State Electronics, 2015

In this manuscript, we have investigated the negative bias temperature instability (NBTI) induced bordertrap (N bt) depth in the interfacial oxide region of PMOS transistors using multi-frequency charge pumping (MFCP) method. We emphasize on the distribution of the permanent component in the oxide near the interface, giving a clear insight on its effect on NBTI features. According to the experimental data, the extracted effective dipole moment (a eff) and field-independent activation energy (E a) have revealed a linear relation with depth distance (Z), which consistently explain the variation of n as well as E a,eff often reported in the literature. In fact, a eff and E a increase with the depth, indicating the presence of the precursor defects having different effective dipole moments and activation energies. We suggest that such traps are most likely related to O 3Àx Si x Si-H (x = 1 and x = 2) family defects (or P b center hydrogen complex) located in the interfacial sub-oxide region.