An empirical large signal model for silicon carbide MESFETs

An Empirical Large Signal Model for Silicon Carbide MESFETs Ahmed Sayed and Georg Boeck Technische Universitaet Berlin, Microwave Engineering Group, HFT 5-1, Einsteinufer 25, 10587 Berlin, Germany, [email protected], Tel. +49 30 31 42 68 95, Fax. +49 30 31 42 68 93 Our approach is based on a multiple bias small signal model. The extrinsic elements of the small signal model are extracted from cold-FET operation whereas the intrinsic parameters are calculated directly from measured network parameters at various bias points [4]. The equivalent circuit of the proposed nonlinear model is shown in Fig. 1. The nonlinear elements are the gate-drain diode dgd, the gatesource diode dgs, the static drain current source IdsDC, the gatesource capacitance Cgs, the gate-drain capacitance Cgd, the drain-source capacitance Cds as well as the dispersion current source IdsRF. CPGD dgd LG Gate C gd RG R gd RD C PG Cgs R gs RC CPD CRF RS LS + Tth Ith - Fig. 1. LD Drain dgs Cds Silicon carbide (SiC) has received remarkable attention during the last decade as a promising material for high power, high frequency, high temperature device applications due to its high thermal conductivity and high breakdown voltage. Furthermore, application of SiC-MESFETs simplifies impedance matching and results in efficient power coupling and broad bandwidth compared to Si and GaAs devices [1]. The interest in power amplifier design based on this technology necessitates the development of accurate large signal models that can predict the maximum output power level, achievable power added efficiency (PAE), intermodulation behavior and other nonlinear phenomena over the whole bias and frequency range, using harmonic balance (HB) simulation. Today, empirical table-based models are the most widely used models in nonlinear circuit simulators which have the advantage of high flexibility and computation efficiency. A lot of empirical nonlinear MESFET models for microwave circuit simulators have been developed, e.g. [2, 3]. In this approach, the tabulated data that represent the extracted nonlinear elements of the small signal model are mathematically transformed into spline functions which should be differentiable to a high order of derivatives in order to ensure a correct description of harmonics and convergence applying harmonic balance simulations [3]. As an extension to the previous authors’ work given in [4, 5], an empirical model based on SiC MESFET has been developed and verified. This paper is organized as follows: Sec. II presents the model incorporating empirical expressions for DC, capacitance and frequency dispersion. The accuracy of the new model will be verified in Sec. III. Based on the derived model, a single stage II. MODEL DESCRIPTION IdsRF I. INTRODUCTION ultra wideband PA has been designed and small signal as well as large signal simulations and measurements have been demonstrated. The conclusion of the work is given in Sec. IV. IdsDC Abstract — In this paper, a large signal table-based model for SiC MESFET is presented. A packaged commercially available high power MESFET device (CREE CRF24010) is adopted for the model development. The extracted bias-dependent elements of the small signal model as well as the measured DC data are mathematically described by small modification of Angelov’s formulation. Dispersion between DC and RF characteristics of the drain current is also observed and interpreted. The new model is capable to predict small signal as well as large signal performance accurately. A single stage ultra broadband 5 W power amplifier has been developed to verify the derived model. A good agreement has been obtained between simulated and measured results. R th C th + T - 0 Large signal model of SiC MESFET. A. Drain Current Modeling The DC characteristics of the presented model are based on the approach by Angelov [3]. We use a slightly modified saturation voltage parameter D to match the measured data of the SiC device: D D r  D1 (D 2  tanh(\ )) (1) The model has been implemented in ADS from Agilent. Measured and simulated DC characteristics for the Cree SiC MESFET device CRF24010 are shown in Fig. 2. Excellent agreement between measurements and calculations could be achieved over a wide bias range Vds up to 60 V and Vgs between –13 V and –5 V. The small letters (ds) and (gs) 13th GAAS Symposium - Paris, 2005 313 3.5 indicate intrinsic device voltages. The device was mounted on a heat sink during the measurements providing a ground plate temperature of the device package of about 20°C. Cgs (pF) 1.2 3.0 Meas. Calc. 0.8 2.5 2.0 ID (A) 1.5 1.0 0.4 0 5 10 15 20 25 30 Vds (V) 0.0 0 10 20 30 40 50 60 V ds (V) Fig. 2. Measured (symbols) and calculated (solid lines) DC characteristics of the SiC MESFET device CRF24010, Vgs = - 13 V to - 5 V, step 1 V. Table 1 gives an enhanced comparison of the DC model quality with state of the art work. The values of the error function (Table 1) indicate that our model achieves the lowest values of the error function compared with other CAD models. Table 1. Comparison of the error function values of the most used CAD models in ADS. Model Curtice-Ettenberg model [8] Error Materka-Kacprzak model [7] Statz model [6] 8.2e -4 7.14e TOM3 model [9] 2.9e Our model 2e -3 -4 4e -4 -5 B. Capacitance Modeling Capacitance modeling becomes more and more important if operating frequencies increase. At higher frequencies nonlinear capacitances have a raising influence on frequency response, harmonic and intermodulation distortion. There are two main approaches for modeling of the gate charge, the capacitance and charge approach. We use the capacitive approach and describe the capacitance voltage characteristics of the device. Again, the formulation used here is similar to the model of Angelov et al [3]. Both capacitances show a dual voltage dependence and integration path independency of the capacitance functions has been verified. Unique charge functions and charge conservation are guaranteed this way which are very important suppositions for stable and reliable harmonic balance simulations. As an example for the capacitance modeling the extracted and modeled gate source capacitance Cgs versus Vds (parameter Vgs) is shown in Fig. 3. A very satisfactory agreement between measured and simulated data can be observed. 314 Fig. 3. Measured (symbols) and modeled (solid lines) gate-source capacitance Cgs versus Vds, Vgs varies from - 13 V (bottom) to - 6 V (top), step 1 V. C. Frequency Dispersion and Thermal Modeling Measurements at the SiC device have shown that the RF current characteristics are different from DC ones (low frequency dispersion) done by deep level trapping. This behavior can be described by using two different drain current sources one for the low frequency and one for the RF range, respectively. E. g., the RF current source can be obtained by integration the small signal transconductance gm and output conductance gds, respectively: I dsRF ³ g m dVgs  g ds dVds (2) One way to eliminate the differences between high- and low-frequency output conductances is to add a capacitive coupled resistive branch (RC, CRF) to the output as shown in Fig. 1. The introduction of smoothing functions for matching the differences between low and high frequency operation would be another approach [10]. The resistance RC is selected to be a bias dependent hyperbolic function in order to eliminate dispersion effects in the entire large signal range. This is important with respect to the ability of the model to predict the nonlinear behavior in the whole operating range with high accuracy and reliability. RC RC min  K 1 (1  1 / RC max  K 2 tanh(\ )) (3) RCmin and RCmax represent the minimum and the maximum dispersion resistances, respectively andK1, K2 and \ are functions of Vgs, Vds. The parameters of (3) are being found by optimization of S22 at several bias points. Verification of frequency dispersion modeling is finally demonstrated in Fig. 4. A dynamic thermal model is introduced, too. A low-pass structure which accounts for self-heating effects is shown in Fig. 1. The model based temperature behavior is presented in Sec. III. III. MODEL VERIFICATION The proposed model has been implemented as a userdefined model into the harmonic balance circuit simulator 13th GAAS Symposium - Paris, 2005 30 OIP2, OIP3 (dBm) (dBm), G (dB) 80 Pout out V gs 20 OIP2 0 0 4 10 5 6 10 f (Hz) 10 7 10 8 10 40 Fig. 4. Dispersion of the output conductance at Vds = 30 V and Vgs = – 11 V to – 6 V, step 1 V. 50 40 40 Pout 30 30 20 PAE 10 0 0 20 GP 10 20 30 Input Power (dBm) PAE (%) Output Power (dBm), Gain (dB) For this reason, a single-stage wideband power amplifier has been designed [5], built up and characterized using the Cree SiC MESFET CRF24010. A heat sink was used during the experiments so that the device temperature was very close to room temperature. In contrast to [5], in this work the verification of the large signal performance of the model (not of the amplifier) is the main goal. The large signal model presented here was not available at publication time of [5]. Simulated and measured power performances of the designed power amplifier are compared in Fig. 4 at 1 GHz. Excellent agreement has been achieved for output power (Pout) and power gain (GP). A 1 dBCP of 37 dBm can be taken from Fig. 5. With respect to the PAE performance, 1 % error for maximum PAE value can be observed. 50 GP 0.5 1 1.5 f (GHz) 2 20 2.5 9 10 0 40 Fig. 5. Measured (symbols) and simulated power performance of the designed PA based on the derived model (solid lines): f = 1 GHz, Vds = 30 V, ID = 500 mA. Over the whole frequency band (10 MHz – 2.4 GHz), the power performance as well as the linearity performance (twotone test) of the designed amplifier have been characterized and compared with simulations based on the proposed model. Fig. 6. Measured (symbols) and simulated power and linearity performances of single stage PA over the operating frequency range: Vds = 30 V, ID = 500 mA and ' = 200 kHz. Fig. 6 illustrates the overall simulated and measured performances versus frequency. Regarding the power performance, excellent agreement between simulations and measurements has been achieved. On the other hand, slight differences of 4 dBm and 2 dBm between the measured and modeled second- and third-order output intercept points (OIP2 and OIP3) respectively, can be observed. The impact of case temperature variation has been studied, too. Fig. 7 shows the simulated and the measured power performance of the single stage PA versus temperature. A good agreement can be noticed with only 0.6 dB power gain deviation at 60 °C between simulations and measurements. 9 38 Power (dBm) 10 60 10 12 8 3 10 OIP3 35 Pout GP 8 7 32 29 26 20 6 Pin 40 60 T (°C) 80 Power Gain (dB) 16 P gds (mS) P 20 100 40 ADS from Agilent and large signal performance has been studied as an extension of the work given in [4]. 5 100 Fig. 7. Measured (symbols) and modeled (solid lines) power stage performance versus temperature: f = 1 GHz, Vds = 30 V and ID = 500 mA. In this work we have also investigated the group delay. For minimum distortion the variation of the group delay within the modulation bandwidth has to be as low as possible. Group delay Wis defined as the slope of the transmission phase versus frequency [11] dI (4) W  dZ 13th GAAS Symposium - Paris, 2005 315 where I is the transmission phase in radians, and Z is the radiant frequency in (rad/s). At an input power of 25 dBm, Fig. 8 illustrates the group delay variation over the operating bandwidth of the implemented SiC MESFET power stage. It can be seen that up to 2.5 GHz, a low value of up to 1.4 ns has been achieved. Group Delay (ns) 1.4 1.2 1.0 0.8 0.6 0.0 0.5 1.0 1.5 f (GHz) 2.0 2.5 Fig. 8. Simulated group delay of the implemented model based on SiC MESFET: Pin = 30 dBm, VDS = 30 V and ID = 500 mA. IV. CONCLUSION A new large signal table-based model for SiC MESFETs based on Angelov’s formulation has been developed. Temperature dependence and dispersion effects are included. The new model has been implemented as a user-defined model in the harmonic balance circuit simulator ADS. Based on an implemented single stage PA, the derived model has been verified. Measured small and large signal performances as well as temperature behavior agree pretty well with simulations. 316 REFERENCES [1] S. T. Allen, W. L. Pribble, R. A. Sadler, T. S. Alcorn, Z. Ring and J. W. Palmour, “Progress in high power SiC microwave MESFETs,” IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, Anaheim, CA, pp. 321-324, June 1999. [2] A. Rofougaran and A. A. Abidi, “A table lookup FET model for accurate analog circuit simulation,” IEEE Trans. Microwave Theory and Tech., vol. 47, pp. 2350-2357, Dec. 1999. [3] I. Angelov, N. Rorsman, J. Stenarson, M. Garcia and H. Zirath, “An empirical table-based FET model,” IEEE Trans. Computer Aided Design, vol. 12, pp. 324-335, Feb. 1993. [4] A. Sayed and G. Boeck; “Small signal modeling of SiC power MESFETs for ultra broadband power amplifiers,” 28th WOCSDICE, Slovakia, pp. 79-80, May 2004. [5] A. Sayed, S. von der Mark and G. Boeck, “An ultra wideband power amplifier using SiC MESFETs,” Proc. 34th European Microwave Conf., Amsterdam, Netherlands, Oct. 2004. [6] H. Statz, R. Newman, I. W. Smith, R. A. Pucel, and H. A. Haus, “GaAs FET device and circuit simulation in SPICE,” IEEE Trans. Electron Devices, vol. 34, pp. 160-169, Feb. 1987. [7] T. Kacprzak and A. Materka, “Compact DC model of GaAs FETs for large-signal computer calculation,” IEEE J. SolidState Circuits, vol. Scull, pp. 211–213, April 1983. [8] W. R. Curtice, “A MESFET model for use in the design of GaAs integrated circuits,” IEEE Trans. Microwave Theory Tech., vol. 28, pp. 448–456, May 1980. [9] R. B. Hallgren and P.H. Litzenberg, “TOM3 Capacitance Model: Linking Large- and Small-Signal MESFET Models in SPICE,” IEEE MTT, vol. 47, no. 5, pp. 556-561, May 1999. [10] A. Werthof, “Experimentelle modellierung aktiver bauelemente fuer die simulation nichtlinearer mikrowellenschaltungen,” VDI-Verlag GmbH, Page 189. Duesseldorf 1995. [11] P. Vizmuller, “RF Design Guide: Systems, Circuits, and equations,” Artec House, Inc, 1995. 13th GAAS Symposium - Paris, 2005