Papers by Mayank Chakraverty
Advanced Materials Research
The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a var... more The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, thi...
Journal of Biomedical Materials Research Part B: Applied Biomaterials, 2009
Carbonated hydroxyapatite (CHA) bone cement is capable of self-setting and forming structures sim... more Carbonated hydroxyapatite (CHA) bone cement is capable of self-setting and forming structures similar to mineralized bone. Conventional CHA leaves little room for new bone formation and delays remodeling. The purposes of this study were to develop porous CHA (PCHA) bone cement and to investigate its physicochemical properties, biocompatibility, biodegradation, and in vivo bone repair potential. Vesicants were added to modify CHA, and the solidification time, porosity, and pore size of the PCHA cements were examined. The cytotoxicity and bone repair potential of PCHA were tested in a rabbit bone defect model and assessed by x-ray, histological examination, and mechanical testing. The porosity of the modified PCHA was 36%; 90.23% of the pores were greater than 70 lm, with a calcium/ phosphate ratio of 1.64 and a solidification time of 15 minutes. The PCHA did not affect bone cell growth in vitro, and the degrading time of the PCHA was two and four times faster in vitro and in vivo when compared to CHA. In the bone defect model, the amount of new bone formation in the PCHA-treated group was eight times greater than that of the CHA group; the compressive strength of the PCHA setting was relatively weak in the first weeks but increased significantly at 8 to 16 weeks compared to the CHA group. The PCHA has stable physicochemical properties and excellent biocompatibility; it degrades faster than CHA, provides more porous spaces for new bone ingrowths, and may be a new form of bone cement for the management of bone defects.
Cornell University - arXiv, Jul 9, 2014
At the very outset, I take the opportunity to thank Almighty for showering his choicest blessings... more At the very outset, I take the opportunity to thank Almighty for showering his choicest blessings on a little mortal like me. But for his I would not have overcome the several odds that came in my way. I thank the Security, Governance, Risk & Compliance (SGRC) practice under GBS Business Unit and Semiconductor Research & Development Center under STG Business Unit, IBM, Bangalore, for giving me an opportunity to carry out my studies and successfully complete this project work along with my deliverables and assignments at office. I take the opportunity to thank Manipal University, Manipal, India for providing their approval to go ahead with this project. With deep sense of gratitude I thank all the faculty members of Centre for
Materials Science Forum, 2022
This paper demonstrates the transport of electron and hole carriers in two distinct hydrogenated ... more This paper demonstrates the transport of electron and hole carriers in two distinct hydrogenated amorphous semiconductor materials at different temperatures. Compared to crystalline materials, the amorphous semiconductors differ structurally, optically and electrically, hence the nature of carrier transport through such amorphous materials differ. Materials like hydrogenated amorphous silicon and amorphous IGZO have been used for the study of temperature dependent carrier transport in this paper. Simulation results have been presented to show the variation of free electron and hole concentration, trapped electron and hole concentration with energy at 300K for both the materials. The change in mobility with a change in the Fermi level has been plotted for different temperatures. The effect of temperature on Brownian motion mobility of electrons and holes in hydrogenated amorphous silicon and amorphous IGZO has been demonstrated towards the end of this paper.
Handbook for III-V High Electron Mobility Transistor Technologies, 2019
This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RA... more This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RAM for use in cell phone architectures by replacing age old flash memories through a series of simulations performed using various tools. Magnetoresistive memory (MRAM) is one of the forerunners of the nanotechnology enabled memories lined to replace the traditional memories like Flash, DRAM and SRAM. MRAMs are based on the phenomenon of spin dependent tunneling in magnetic tunnel junctions (MTJs). It stores data in the magnetization of a magnetic layer as opposed to electrical charge in conventional RAMs. Yet the read-out of the MRAM is electrical. It is claimed to offer something close to the speed of SRAM, with a density approaching that of single-transistor DRAM and the ability to store information when power is removed, like flash memory or EEPROM.
Materials Today: Proceedings, 2021
Materials Today: Proceedings, 2020
Though the concept of the thin film device, known by the name, memristors, as coined by Leon Chua... more Though the concept of the thin film device, known by the name, memristors, as coined by Leon Chua, was theorized in 1971, it was only from the year 2008 that these thin film devices gained broader attention when R. Stanley Williams and his team demonstrated the first practical realization of the memristor at the HP labs. Memristors have been considered as the fourth fundamental circuit element, adding to resistors, capacitors and inductors. Among several other applications, the most unique application of memristors is that, while they occupy very little chip area, the synapses in the brain can be closely modeled using these devices. The memristive device from HP had two platinum electrodes on either side of a titanium dioxide (TiO 2) and oxygen deficient titanium dioxide (TiO 2-x) layers. The boundary separating the stoichiometric and oxygen deficient TiO 2 regions can be shifted on either side under the effect of an applied electric field. The current-voltage characteristics of this device from HP Labs exhibited a pinched hysteresis loop with a zero-crossing, depicting high resistance and low resistance states distinctly. Since the discovery at HP labs, researchers have reported several material choices for the electrodes and the active region (TiO 2-TiO 2-x). This paper presents a qualitative study on the material aspects of these nanoscale devices. Also, an exhaustive study of the different methodologies for fabricating such memristive systems is presented in this paper. These two terminal devices can be fabricated in a variety of ways but each method of fabrication has its own set of limitations since these devices operate at the nanoscale. The suitability of the single step and two step nano-imprint lithography (NIL) for memristors has been qualitatively examined in this paper.
IOSR Journal of Electronics and Communication Engineering, 2016
Gate All Around (GAA) FET stands out as one of the most promising FET designs to replace the curr... more Gate All Around (GAA) FET stands out as one of the most promising FET designs to replace the currently planar MOSFETs due to its ability to provide better gate control and better immunity to short channel effects. .This paper reports the electrical characteristics of GAA Silicon Nanowire Field Effect Transistor obtained using Extended Huckel Theory based Semi Empirical Method. The physics behind the Semi Empirical method has been presented in brief. The nanowire transistor has been simulated with two different gate dielectrics (SiO 2 & ZrO 2) and the electrical characteristics resulting from the two structures have been compared for power efficiency. A comparison of off-state current and off-state channel conductance between the two nanowire transistor structures has been presented towards the end of the paper that demonstrates that ZrO 2 gate dielectric based silicon nanowire transistor is power efficient than its counterpart with SiO 2 gate dielectric..
International Journal of …, 2010
This Paper presents an analysis of single ended low Noise Amplifier in a transceiver for wireless... more This Paper presents an analysis of single ended low Noise Amplifier in a transceiver for wireless sensor network. The Low Noise Amplifier consumes a Power of 65.9µ W. The Noise analysis for the LNA is achieved for a frequency range of 1GHZ-3GHz.
2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018
This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunne... more This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunnel junctions (MTJs) using first principles SGGA band structure calculations at four different temperatures. The Co-MgO-Co tunnel junction has been simulated at four different temperatures to obtain the I-V and dI/dV-V characteristics with parallel and anti-parallel magnetization states, respectively. The TMR ratios have been computed at all four different temperatures. It is seen that temperature doesn't seem to greatly fluctuate the TMR ratios of this magnetic tunnel junction, thereby making it suitable for applications over a wide range of temperatures. For the same four temperatures, the tunnel junction has been simulated for increasing insulator thicknesses. The exponential increase in resistance in both parallel and antiparallel magnetization states has been observed with an increase in the insulating layer thickness. The effect of increasing insulator thicknesses on the TMR ratios at all the four temperatures has also been presented in this paper. The demonstration of bias dependence of tunneling magnetoresistance presented in this paper aptly justifies the application of Co-MgO-Co MTJs in Magnetoresistive Random Access Memories.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetores... more Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetoresistance (TMR) ratios. In this work, we present the results of First Principle simulations of Fe/ MgO/Fe MTJs with LSDA as the exchange correlation. The I-V characteristics in the antiparallel magnetization state exhibit strong features. The bias dependence of the TMR ratio shows nearly 100% TMR ratios for bias voltages up to 1.5 Volts. The MgO thickness dependence of the tunnel resistance shows the expected exponential increase in the tunnel resistance. The write energy per bit and power consumption have been computed for a bias voltage of 0.5 Volts. The Fe/MgO/Fe MTJs are the most widely used MTJs, integrated with NMOS transistors, in the form of MTJ based Magnetoresistive Random Access Memory (MRAM) which is an advanced memory technology operating at the nano scale. MRAMs are spintronic devices.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
The effect of process and temperature variations are becoming more dominant with technology scali... more The effect of process and temperature variations are becoming more dominant with technology scaling, especially for RF circuits, wherein even the minute variability in FETs and passive devices have a significant impact on the overall circuit behavior. Due to stringent power and performance specification requirements in the latest Wireless/RF applications, reasonable compensation for the process, voltage and temperature variations, is even more critical. In this paper, the design of a 2.4GHz operated, ultra-low power CMOS down-converting active mixer fabricated in standard 180 nm RF CMOS technology has been presented. The mixer is based on double balanced Gilbert-cell resistor-loaded topology. The effects of process and temperature variations on the designed mixer have been investigated and various compensation techniques relevant to the current design have been analyzed.
There are various commercially available Analog/RF simulator tools currently in the market, which... more There are various commercially available Analog/RF simulator tools currently in the market, which have their distinctive applications and advantages. In this paper, some of the most widely used Analog/RF simulators (Cadence Spectre/APS, Keysight ADS and GoldenGate, and Mentor Graphics AFS) have been reviewed with respect to their performance and unique features. An LC-VCO and a CMOS Ring Oscillator are designed using GLOBALFOUNDRIES 45 nm RFSOI technology PDK. They are simulated using all the four listed simulators and their results have been analyzed with respect to performance and circuit design aspects.
Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law int... more Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at the end of the paper justifies the theory of nanowire FETs to carry forward the downscaling of MOSFETs in the sub-10 nm regime. Keywords: Nanowire, scaling, MOSFET, VLS, nanoelectronics, short channel effects (SCEs), density of states, SiNWFET Cite this Article Chakraverty Mayank, Gupta Kinshuk, Babu Vinay G. et al. A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design. Journal of Nanoscience, Nanoengineering and Appl...
With rapid advancements in the technology arena, novel design methodologies have been embraced an... more With rapid advancements in the technology arena, novel design methodologies have been embraced and to support these requirements, semiconductor process technology is also rapidly evolving. There is a need for efficient handshake between the foundry and design houses. PDKs play an important role in inheriting the foundry offering to aid in successful silicon realization. This paper presents an overview of process design kits and the importance of well-crafted kits in niche RF IC designs. The chip design ecosystem has been pictorially explained while emphasizing on the role of a foundry in the ecosystem. The different components of the process design kit have been discussed in brief. The method of qualification of process design kits and the various quality enhancement approaches to enable first pass silicon success have been presented in this paper. Towards the end of the paper, different substrate methodologies adopted by foundries for RF designs have been presented at a high level.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
Reduction of power consumption in battery-powered and portable VLSI systems has become an importa... more Reduction of power consumption in battery-powered and portable VLSI systems has become an important aspect in system design. The various sources of power dissipation have been discussed in this paper. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy through different levels including technology, layout, circuit, logic, architecture, software and system levels. A review of low-power techniques applied at logic and architecture levels of the design hierarchy has been presented in detail in this paper, with some of the design decisions made for the implementation of VLSI system.
Advanced Science, Engineering and Medicine, 2016
The exponential pace of transistor evolution has led to a revolution in information acquisition, ... more The exponential pace of transistor evolution has led to a revolution in information acquisition, processing and communication technologies. And reigning over most digital applications is a single device structure—the field-effect transistor (FET). But as device dimensions approach the nanometer scale, quantum effects become increasingly important for device operation, and conceptually new transistor structures may need to be adopted. A notable example of such a structure is the single-electron transistor, or SET. Although it is unlikely that SETs will replace FETs in conventional electronics, they would prove useful in ultra-low-noise analog applications. Moreover, because it is not affected by the same technological limitations as the FETs, the SET can approach closely the quantum limit of sensitivity. It might also be a useful read-out device for a solid-state quantum computer. In this paper, the I–V characteristics of an SET have been simulated and a variation of the threshold voltage of the device has been experimentally observed with the gate voltage.Also, an empirical relation of threshold voltage with electrochemical potential of the island has been proposed in this paper.
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Papers by Mayank Chakraverty