Analog integrated circuits operating in radiation environments. In previous irradiation experimen... more Analog integrated circuits operating in radiation environments. In previous irradiation experiments performed on a switched-capacitor filter, implemented in a programmable analog array, it was observed a sudden recovery of the device performance during the irradiation, while increasing the accumulated dose. In some cases the considered performance parameters (such as the total harmonic distortion) may even be enhanced if compared to the pre-irradiation measurements, in specific accumulated dose intervals. This behavior is associated to partial inactivity windows in the internal components of the device. Spice simulations considering two complementary architectures of a simple CMOS Operational Amplifier (OpAmp) are performed, aiming to understand the origins of this effect. Results indicate that shifts on the operating point of the amplifier building blocks are responsible for the degradation and recovery of the OpAmp performance. Results also show that specific architectures, as wel...
Resumo: O Teste é parte determinante do ciclo de concepção de sistemas eletrônicos e circuitos in... more Resumo: O Teste é parte determinante do ciclo de concepção de sistemas eletrônicos e circuitos integrados. Responsável pela qualidade e pela realimentação das etapas de projeto e do processo de fabricação, o teste tem se tornado tão complexo quanto os próprios circuitos integrados atuais. As principais alternativas para reduzir o impacto do custo do teste no circuito ou sistema final, sem reduzir a qualidade do produto, encontram suporte nas técnicas de autoteste integrado e projeto visando a testabilidade. Neste contexto, este capítulo visa apresentar os principais conceitos que envolvem o teste de sistemas eletrônicos, com ênfase em sistemas integrados, bem como discutir algumas das muitas técnicas de autoteste integrado e projeto visando o teste que vêm sendo utilizadas, com sucesso, ao longo dos últimos anos.
Response Analyzer (ORA) built using the internal FPAA resources. Both approaches are validated us... more Response Analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.
2010 IEEE 16th International On-Line Testing Symposium, 2010
ABSTRACT Programmable analog devices are susceptible to radiation effects. TID effects are a matt... more ABSTRACT Programmable analog devices are susceptible to radiation effects. TID effects are a matter of concern due to the thickness of oxides in common analog technologies and can be mitigated by HBD techniques and shielding. SEEs may also disturb programmable analog devices, and system level techniques based on on-line error detection and self-correction may be applied by using the available programmable resources of the device.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014
Register (SAR) converters based on charge redistribution are often present in embedded mixed-sign... more Register (SAR) converters based on charge redistribution are often present in embedded mixed-signal systems. Previous works have shown that this topology is prone to errors on the conversion, caused by Single Event Transients (SET), when exposed to ionizing radiation. Such errors can propagate to the subsequent steps of conversion, leading to multiple bit errors on the converted data. In this work, the effects of SETs on the analog switches and on the digital control logic of a charge redistribution SAR A/D converter are analyzed. A fault injection framework was developed in a way that faults are randomly injected, by means of spice simulations, considering a 130nm CMOS technology. This way, the behavior of the converter under single event effects can be predicted, and the most vulnerable circuit nodes can be identified.
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, 2014
In this work, we analyze the resilience of SAR converters based on charge redistribution against ... more In this work, we analyze the resilience of SAR converters based on charge redistribution against Single Event Transients. These effects may be mitigated using well-known Fault Tolerance techniques. However, each strategy has its advantages and disadvantages, which may affect the area, power consumption, as well as the linearity of the circuit. This paper shows possible alternatives for the best trade-off approach on the design of such converters. Investigations were conducted by means of an extensive fault injection campaign in an 8-bit architecture modeled in SPICE, considering a 130nm predictive technology model.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT This work presents a study on the effects of Single Event Transients on SAR A/D converte... more ABSTRACT This work presents a study on the effects of Single Event Transients on SAR A/D converters based on charge redistribution. The effects of SETs are analyzed considering the worst-case pulses for the 130nm CMOS process. In this work, the fault injection is concentrated on the switches of the capacitor array of the studied converter. Preliminary results show that the transient effects may change the state of one or more bits of conversion. This is due the fact that the affected stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Moreover, a SET occurring on the switch connected to the common node of the capacitors may lead to an incorrect behavior that cannot be attenuated with the increasing on the sizing of the transistors, which suggests that additional fault tolerance techniques may be needed.
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT This paper describes a neutron-induced single event effect test in analog-to-digital con... more ABSTRACT This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemi's programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successive approximation register architecture of the analog-to-digital converters (SAR-ADC) embedded into this device, considering critical application projects. The case-study circuit is a data acquisition system that uses the two available analog-to-digital converters (ADCs), being one converter controlled by the embedded processor and the other by the digital programmable matrix of the device. This scheme is based on a design diversity redundancy concept. The setup was exposed to a neutron source at the CCLRC Rutherford Appleton Laboratory - ISIS in order to investigate the occurrence of SEEs ranging from single to errors bursts. Also, SPICE simulations were carried out in a charge redistribution SAR-ADC architecture in order to clarify the results obtained from this experiment.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
ABSTRACT In this work the problem of single event upset (SEU) is considered to a new analog techn... more ABSTRACT In this work the problem of single event upset (SEU) is considered to a new analog technology: the field programmable analog arrays (FPAAs). Some FPAA models are based on SRAM memory cells to implement the user programmability. For this reason, such kind of device becomes vulnerable to SEU when employed in applications susceptible to the incidence of electrical charged particles. In the former part of this work some fault injection experiments are made in order to investigate the effects of SEU in the SRAM blocks of a commercial FPAA. For this purpose, single bit inversions are injected in the FPAA programming bit-stream. In a second moment, a self-recovering scheme using the studied FPAA is proposed. This scheme is able to restore the original programming data if an error is detected. The error detection circuit is built using the internal programming resources of the FPAA and a very simple external logic.
ABSTRACT Radiation effects translated into Single Event Transients (SETs) and Single Event Upsets... more ABSTRACT Radiation effects translated into Single Event Transients (SETs) and Single Event Upsets (SEUs) are dealt with, in this chapter, in the realm of analog and mixed-signal circuits. First of all, we revisit concepts and methods of the analog testing field looking for techniques that may help mitigating, at the system level, SETs and SEUs in these circuits. Then, two mixed-signal case studies are presented. The first case study investigates the effects of SEUs in a new kind of analog circuit: the Field Programmable Analog Arrays (FPAAs). Some FPAA devices are based on SRAM memory cells to implement the user programmability. For this reason the effect of radiation in such circuits can be as dangerous as it is for FPGAs. BIT-flip experiments are performed in a commercial FPAA, and the obtained results show that a single BIT inversion can result in a very different configuration of that previously programmed into the device. The second case study is focused on ΣΔ A/D Converters. A MatLab-based model of such converter is built and a series of fault injection experiments is performed. The results show that the ΣΔ converter can be used in radiation environment, if its digital part is protected. Such protection can be achieved by adopting some design directives. This chapter ends by proposing the use of online analog test methods, in particular self-checking circuits, that can be applied to detect SET and SEU faults during the circuit operation, therefore allowing the design of self-recovering systems.
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT This paper presents an investigation on the performance of analog building-blocks of two... more ABSTRACT This paper presents an investigation on the performance of analog building-blocks of two counterpart architectures of Operational Amplifiers (with PMOS and NMOS differential amplifier as input stage) under cumulative radiation effects. This investigation is performed through Spice simulations, by injecting typical radiation-induced shifts in the threshold voltage of the transistors for the considered technology, a 0.5 µm standard CMOS process. Transient and DC (Direct Current) analysis are performed in differential and inverter stages of a simple two-stage operational amplifier. The linearity and voltage swing of both amplifier stages are evaluated, as well as, the effects on the bias current and the output offset voltage. Simulation results show that the NMOS differential amplifier architecture may have an improved robustness in radiation environments, if compared to its PMOS counterpart, when considering the typical behavior of MOS transistors under radiation.
2011 12th Latin American Test Workshop (LATW), 2011
Capacitor Arrays (PCA) are investigated. Usually, PCA architectures are built from a set of binar... more Capacitor Arrays (PCA) are investigated. Usually, PCA architectures are built from a set of binary-weighted capacitor branches, which can be connected in parallel. The connection of each branch to the terminals of the capacitor array is programmed through analog switches (usually transmission gates). Transient faults, potentially caused by radiation interaction with the silicon, or by the impact of strongly ionizing particles in sensitive nodes, may temporarily close a switch in the PCA, whose default state should be open. In this case, it may occur a charge sharing process, from the equivalent capacitor (programmed into the PCA) to the temporarily connected capacitor (due to the transient effect). Therefore, after the transient, the voltage stored in the equivalent capacitor may be reduced. This effect is investigated with spice simulations. The influence of the values of the capacitors and the sizing of the analog switches (and its control logic) in the magnitude of the charge sharing effect is also investigated. Finally, some possible design-level mitigation techniques are discussed.
ABSTRACT We exposed a mixed-signal system-on-chip to gamma radiation in order to measure variatio... more ABSTRACT We exposed a mixed-signal system-on-chip to gamma radiation in order to measure variations in current, temperature and propagation-delay in its components, such as configurable array, embedded analog blocks and microprocessor.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT Due to the technology scaling of modern integrated circuits, the electronic systems are ... more ABSTRACT Due to the technology scaling of modern integrated circuits, the electronic systems are increasingly become more susceptible to transient faults, potentially caused by radiation interaction with the semiconductor. Furthermore the variability of production process, associated to this scaling, and the increase on the operating frequencies, lead to an increaseon the probability of faults of complex circuits. This work addresses the concepts of redundancy and diversity with the DTMR technique to improve the fault tolerance of a data acquisition system. A physical implementation is made using a Programmable SoC from Cypress Semiconductor. Results indicate that the system is effective to tolerate single, double and multiple bit-flip faults.
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, 2014
In this work a novel radiation tolerance technique based on modular redundancy, associated to an ... more In this work a novel radiation tolerance technique based on modular redundancy, associated to an alternated biasing scheme, is presented. The goal of this technique is to extend electronic systems lifetime in radiation environments for circuits that are susceptible to TID effects. In order to validate this technique, a board level prototype was built, considering an FPAA (Field Programmable Analog Array) as Device Under Test (DUT), to which the concept was applied. The prototype was exposed to Co60 gamma radiation with a dose rate of 1krad(Si)/h. Results show that devices that are alternated biased are able to tolerate higher accumulated doses than the one that is permanently biased.
Analog integrated circuits operating in radiation environments. In previous irradiation experimen... more Analog integrated circuits operating in radiation environments. In previous irradiation experiments performed on a switched-capacitor filter, implemented in a programmable analog array, it was observed a sudden recovery of the device performance during the irradiation, while increasing the accumulated dose. In some cases the considered performance parameters (such as the total harmonic distortion) may even be enhanced if compared to the pre-irradiation measurements, in specific accumulated dose intervals. This behavior is associated to partial inactivity windows in the internal components of the device. Spice simulations considering two complementary architectures of a simple CMOS Operational Amplifier (OpAmp) are performed, aiming to understand the origins of this effect. Results indicate that shifts on the operating point of the amplifier building blocks are responsible for the degradation and recovery of the OpAmp performance. Results also show that specific architectures, as wel...
Resumo: O Teste é parte determinante do ciclo de concepção de sistemas eletrônicos e circuitos in... more Resumo: O Teste é parte determinante do ciclo de concepção de sistemas eletrônicos e circuitos integrados. Responsável pela qualidade e pela realimentação das etapas de projeto e do processo de fabricação, o teste tem se tornado tão complexo quanto os próprios circuitos integrados atuais. As principais alternativas para reduzir o impacto do custo do teste no circuito ou sistema final, sem reduzir a qualidade do produto, encontram suporte nas técnicas de autoteste integrado e projeto visando a testabilidade. Neste contexto, este capítulo visa apresentar os principais conceitos que envolvem o teste de sistemas eletrônicos, com ênfase em sistemas integrados, bem como discutir algumas das muitas técnicas de autoteste integrado e projeto visando o teste que vêm sendo utilizadas, com sucesso, ao longo dos últimos anos.
Response Analyzer (ORA) built using the internal FPAA resources. Both approaches are validated us... more Response Analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.
2010 IEEE 16th International On-Line Testing Symposium, 2010
ABSTRACT Programmable analog devices are susceptible to radiation effects. TID effects are a matt... more ABSTRACT Programmable analog devices are susceptible to radiation effects. TID effects are a matter of concern due to the thickness of oxides in common analog technologies and can be mitigated by HBD techniques and shielding. SEEs may also disturb programmable analog devices, and system level techniques based on on-line error detection and self-correction may be applied by using the available programmable resources of the device.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014
Register (SAR) converters based on charge redistribution are often present in embedded mixed-sign... more Register (SAR) converters based on charge redistribution are often present in embedded mixed-signal systems. Previous works have shown that this topology is prone to errors on the conversion, caused by Single Event Transients (SET), when exposed to ionizing radiation. Such errors can propagate to the subsequent steps of conversion, leading to multiple bit errors on the converted data. In this work, the effects of SETs on the analog switches and on the digital control logic of a charge redistribution SAR A/D converter are analyzed. A fault injection framework was developed in a way that faults are randomly injected, by means of spice simulations, considering a 130nm CMOS technology. This way, the behavior of the converter under single event effects can be predicted, and the most vulnerable circuit nodes can be identified.
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, 2014
In this work, we analyze the resilience of SAR converters based on charge redistribution against ... more In this work, we analyze the resilience of SAR converters based on charge redistribution against Single Event Transients. These effects may be mitigated using well-known Fault Tolerance techniques. However, each strategy has its advantages and disadvantages, which may affect the area, power consumption, as well as the linearity of the circuit. This paper shows possible alternatives for the best trade-off approach on the design of such converters. Investigations were conducted by means of an extensive fault injection campaign in an 8-bit architecture modeled in SPICE, considering a 130nm predictive technology model.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT This work presents a study on the effects of Single Event Transients on SAR A/D converte... more ABSTRACT This work presents a study on the effects of Single Event Transients on SAR A/D converters based on charge redistribution. The effects of SETs are analyzed considering the worst-case pulses for the 130nm CMOS process. In this work, the fault injection is concentrated on the switches of the capacitor array of the studied converter. Preliminary results show that the transient effects may change the state of one or more bits of conversion. This is due the fact that the affected stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Moreover, a SET occurring on the switch connected to the common node of the capacitors may lead to an incorrect behavior that cannot be attenuated with the increasing on the sizing of the transistors, which suggests that additional fault tolerance techniques may be needed.
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT This paper describes a neutron-induced single event effect test in analog-to-digital con... more ABSTRACT This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemi's programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successive approximation register architecture of the analog-to-digital converters (SAR-ADC) embedded into this device, considering critical application projects. The case-study circuit is a data acquisition system that uses the two available analog-to-digital converters (ADCs), being one converter controlled by the embedded processor and the other by the digital programmable matrix of the device. This scheme is based on a design diversity redundancy concept. The setup was exposed to a neutron source at the CCLRC Rutherford Appleton Laboratory - ISIS in order to investigate the occurrence of SEEs ranging from single to errors bursts. Also, SPICE simulations were carried out in a charge redistribution SAR-ADC architecture in order to clarify the results obtained from this experiment.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
ABSTRACT In this work the problem of single event upset (SEU) is considered to a new analog techn... more ABSTRACT In this work the problem of single event upset (SEU) is considered to a new analog technology: the field programmable analog arrays (FPAAs). Some FPAA models are based on SRAM memory cells to implement the user programmability. For this reason, such kind of device becomes vulnerable to SEU when employed in applications susceptible to the incidence of electrical charged particles. In the former part of this work some fault injection experiments are made in order to investigate the effects of SEU in the SRAM blocks of a commercial FPAA. For this purpose, single bit inversions are injected in the FPAA programming bit-stream. In a second moment, a self-recovering scheme using the studied FPAA is proposed. This scheme is able to restore the original programming data if an error is detected. The error detection circuit is built using the internal programming resources of the FPAA and a very simple external logic.
ABSTRACT Radiation effects translated into Single Event Transients (SETs) and Single Event Upsets... more ABSTRACT Radiation effects translated into Single Event Transients (SETs) and Single Event Upsets (SEUs) are dealt with, in this chapter, in the realm of analog and mixed-signal circuits. First of all, we revisit concepts and methods of the analog testing field looking for techniques that may help mitigating, at the system level, SETs and SEUs in these circuits. Then, two mixed-signal case studies are presented. The first case study investigates the effects of SEUs in a new kind of analog circuit: the Field Programmable Analog Arrays (FPAAs). Some FPAA devices are based on SRAM memory cells to implement the user programmability. For this reason the effect of radiation in such circuits can be as dangerous as it is for FPGAs. BIT-flip experiments are performed in a commercial FPAA, and the obtained results show that a single BIT inversion can result in a very different configuration of that previously programmed into the device. The second case study is focused on ΣΔ A/D Converters. A MatLab-based model of such converter is built and a series of fault injection experiments is performed. The results show that the ΣΔ converter can be used in radiation environment, if its digital part is protected. Such protection can be achieved by adopting some design directives. This chapter ends by proposing the use of online analog test methods, in particular self-checking circuits, that can be applied to detect SET and SEU faults during the circuit operation, therefore allowing the design of self-recovering systems.
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT This paper presents an investigation on the performance of analog building-blocks of two... more ABSTRACT This paper presents an investigation on the performance of analog building-blocks of two counterpart architectures of Operational Amplifiers (with PMOS and NMOS differential amplifier as input stage) under cumulative radiation effects. This investigation is performed through Spice simulations, by injecting typical radiation-induced shifts in the threshold voltage of the transistors for the considered technology, a 0.5 µm standard CMOS process. Transient and DC (Direct Current) analysis are performed in differential and inverter stages of a simple two-stage operational amplifier. The linearity and voltage swing of both amplifier stages are evaluated, as well as, the effects on the bias current and the output offset voltage. Simulation results show that the NMOS differential amplifier architecture may have an improved robustness in radiation environments, if compared to its PMOS counterpart, when considering the typical behavior of MOS transistors under radiation.
2011 12th Latin American Test Workshop (LATW), 2011
Capacitor Arrays (PCA) are investigated. Usually, PCA architectures are built from a set of binar... more Capacitor Arrays (PCA) are investigated. Usually, PCA architectures are built from a set of binary-weighted capacitor branches, which can be connected in parallel. The connection of each branch to the terminals of the capacitor array is programmed through analog switches (usually transmission gates). Transient faults, potentially caused by radiation interaction with the silicon, or by the impact of strongly ionizing particles in sensitive nodes, may temporarily close a switch in the PCA, whose default state should be open. In this case, it may occur a charge sharing process, from the equivalent capacitor (programmed into the PCA) to the temporarily connected capacitor (due to the transient effect). Therefore, after the transient, the voltage stored in the equivalent capacitor may be reduced. This effect is investigated with spice simulations. The influence of the values of the capacitors and the sizing of the analog switches (and its control logic) in the magnitude of the charge sharing effect is also investigated. Finally, some possible design-level mitigation techniques are discussed.
ABSTRACT We exposed a mixed-signal system-on-chip to gamma radiation in order to measure variatio... more ABSTRACT We exposed a mixed-signal system-on-chip to gamma radiation in order to measure variations in current, temperature and propagation-delay in its components, such as configurable array, embedded analog blocks and microprocessor.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT Due to the technology scaling of modern integrated circuits, the electronic systems are ... more ABSTRACT Due to the technology scaling of modern integrated circuits, the electronic systems are increasingly become more susceptible to transient faults, potentially caused by radiation interaction with the semiconductor. Furthermore the variability of production process, associated to this scaling, and the increase on the operating frequencies, lead to an increaseon the probability of faults of complex circuits. This work addresses the concepts of redundancy and diversity with the DTMR technique to improve the fault tolerance of a data acquisition system. A physical implementation is made using a Programmable SoC from Cypress Semiconductor. Results indicate that the system is effective to tolerate single, double and multiple bit-flip faults.
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, 2014
In this work a novel radiation tolerance technique based on modular redundancy, associated to an ... more In this work a novel radiation tolerance technique based on modular redundancy, associated to an alternated biasing scheme, is presented. The goal of this technique is to extend electronic systems lifetime in radiation environments for circuits that are susceptible to TID effects. In order to validate this technique, a board level prototype was built, considering an FPAA (Field Programmable Analog Array) as Device Under Test (DUT), to which the concept was applied. The prototype was exposed to Co60 gamma radiation with a dose rate of 1krad(Si)/h. Results show that devices that are alternated biased are able to tolerate higher accumulated doses than the one that is permanently biased.
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Papers by Tiago Balen