All Questions
16 questions
0
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114
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In x86_64 architecture, if I modify a PTE in the page table, when will it be sync to TLB?
I am designing an optimistic concurrency control mechanism to address TLB shootdowns for a specific application. The approach operates on the following principles:
The application manages data at the ...
- 1
1
vote
1
answer
284
views
Will an x86_64 CPU notice that a page-table entry has changed to not-present while setting the dirty flag in the PTE?
There is a scenario as follows:
The pte a of PAGE A set following field:
BIT(0) present
BIT(1) writable
BIT(M-1,12) page frame
dirty flag is NOT SET
CPU0 CPU1
...
- 51
2
votes
0
answers
111
views
Is there any way to keep the dirty bit in x86 page tables coherent without TLB invalidates?
The Intel manual contains this admonishment (sec. 4.8):
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see Section 4.10). This fact implies ...
- 560
1
vote
0
answers
140
views
Getting count of TLB misses that resulted in memory access in x86-64
I want to know the number of TLB misses that resulted in memory (DRAM) access. In "Intel(R) Xeon(R) W-2104" system, I can see perf counters like "dtlb_load_misses.miss_causes_a_walk&...
- 422
2
votes
0
answers
467
views
How does a CPU tell if a virtual address is pointing to a huge page? [duplicate]
I'm reading about huge pages in Linux, where the idea is using, say, 2MiB page size instead of 4KiB page size, to reduce TLB misses. I understand that modern CPUs have both data and instruction TLBs, ...
- 9,435
1
vote
1
answer
274
views
Why does my CPU not support 1G-pages although it reports that it does?
When I check CPUID 0x80000001u:EDX:26, I get 1, i.e. my CPU says that it supports 1G-pages. But when I do CPUID 0x80000019u EAX - EDX are zero, i.e. my CPU says that there aren't any large page TLBs (...
- 3,061
6
votes
2
answers
3k
views
Understanding TLB from CPUID results on Intel
I'm exploring leaf 0x02 of the cpuid instruction and came up with a few questions. There is a table in the documentation which describes what cpuid results mean for the TLB configuration. Here they ...
- 27.3k
3
votes
1
answer
296
views
How does the kernel-side page cache virt <-> phys mapping interact with the TLB?
I am writing an application that makes heavy use of mmap, including from distinct processes (not concurrently, but serially). A big determinant of performance is how the TLB is managed user and kernel ...
- 64.6k
3
votes
1
answer
4k
views
How to use INVLPG on x86-64 architecture?
I'm trying to measure memory access timings and need to reduce the noise produced by TLB hits and misses
In order to clear a specific page out of the TLB I tried to use the INVLPG instruction, ...
- 284
6
votes
0
answers
5k
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How to convert virtual address to physical address from user space? Three different methods gave different results in Linux kernel 4x version
First of all, I’m sorry for so long question.
I do some simulation modeling task and I need to translate user space virtual address into kernel space physical addresses. I used three different method ...
- 189
1
vote
1
answer
201
views
cpu TLB - tlb full -> next entry is a miss?
Context:
x86_64, intel core 2 duo.
I searched through the 3 intel doc volumes, and may have missed the right section, hence the question.
A tlb can have up to 4096 entries, that is a lot in my book. ...
- 1,765
27
votes
2
answers
8k
views
When to do or not do INVLPG, MOV to CR3 to minimize TLB flushing
Prologue
I am an operating system hobbyist, and my kernel runs on 80486+, and already supports virtual memory.
Starting from 80386, the x86 processor family by Intel and various clones thereof has ...
5
votes
2
answers
4k
views
TLB usage with multiple page sizes in x86_64 architecture
Does anybody know if TLBs (L1 and L2) support simultaneous accesses with multiple page sizes in modern x86_64 microprocessor (Intel SandyBridge, AMD Bulldozer)? Does x86 core pipeline provides ...
- 743
0
votes
1
answer
512
views
Providing physical address directly to the TLB in x86-64
Is it possible to provide physical address for a given virtual address in a direct way to the TLB on x86-64 architectures in long mode?
For example, lets say, I put zeros in PML4E, so a page fault ...
- 7,322
3
votes
2
answers
3k
views
Dump the contents of TLB buffer of x86 CPU
Is it possible to get list of translations (from virtual pages into physical pages) from TLB (Translation lookaside buffer, this is a special cache in the CPU). I mean modern x86 or x86_64; and I want ...
- 93.8k
7
votes
1
answer
3k
views
How to cause a TLB thrashing with a user process?
My current work needs to generate a specified number of TLB misses on CPU of Intel Core series, while it's not going on well. I've tried many methods but all of them have a very high rate of TLB hit. ...
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