952 questions
-1
votes
1
answer
59
views
Multi Processing vs Multi Threading and Hyper-Threading
What is the difference between thread and process? Threads can use multi core and process use multi core too. Threads shares same memory but process cant share. What if we use shared memory for multi-...
0
votes
0
answers
80
views
Apache NiFi custom processor runtime environment error
I am using NiFi 2.0 that supports python scripts directly from a working directory, after I add my custom processor to the canvas, an error "Processor invalid because initializing runtime ...
- 1
0
votes
0
answers
29
views
comparing the performance of a x86 processor with gem5
I'm trying to create a gem5 implementation that is close to a x86 processor in terms of performance. However, I'm not sure which statistic I can use to compare the performance of the two.
I was ...
- 11
0
votes
0
answers
72
views
Apache Nifi: Add property to Processor which accepts Sensitive Value
Within an Apache Nifi Workflow I would like to create a property which accepts a Sensitive Value.
Via #{password} I would like to assign a parameter from my context parameter to this custom property.
...
- 23
0
votes
0
answers
23
views
Can the processor speculatively fetch instructions in MMIO space?
Why does it say in the instruction manual that speculative instruction fetching can be performed to a certain extent? What's the reason for it? Can the processor speculatively fetch instructions in ...
0
votes
1
answer
78
views
how to call a procedure only after complete data gets ingested
querydatabasetable --> fetch data from source approx 1GB data.
convertavrotojson ---> converting avro fromat data to json format.
splitjson --> splitting a json flowfile into single json ...
- 1
0
votes
0
answers
143
views
Nifi python processor cannot create Relationships in configure processor UI
I created a Python Nifi Processor just as in the standard python documentation. This is NOT an ExecuteScript processor. I am able to load the python processor but when I click the Configure Processor -...
0
votes
1
answer
83
views
how to trigger next processor only after the queue gets empty
querydatabasetable --> fetch data from source approx 2GB data.
convertavrotojson ---> converting avro fromat data to json format
putdatabaserecord --> ingesting all the 2GB (10 million ...
- 1
0
votes
0
answers
150
views
How do i find number of Cycles of a processor?
I am kind of confused on how to find the number of cycles. Although it appears to be pretty simple.
Is it supposed to be number of cycles = (Clock Rate) * (CPI) * (Time)
or
number of cycles = (Clock ...
- 1
0
votes
0
answers
22
views
How add XML2CSV processor to Keboola components?
I would like to use the XML2CSV processor to be able to convert XML files to JSON and then to CSV format.
The problem is that in Keboola Components there is not this component. The only way how to ...
- 1
0
votes
0
answers
26
views
Save Semantic data in GraphDB triplestore using Nifi
I want to save the big semantic data (turtle format), which is transformed via a NiFi processor, in GraphDB. I am using InvokeHTTP in NiFi, but I am not succeeding. I have always Connection timed out (...
- 1
0
votes
1
answer
155
views
No events detected! PAPI 7.1.0 on Ubuntu 22.04
I am trying to use PAPI to check processor events for a college work, but it doesn't show any PAPI Preset Events when use papi_avail -a
After I've already installed libopenmpi-dev, papi-tools and PAPI ...
1
vote
1
answer
132
views
Create dynamic method using Annotation Processor
At the moment I am trying to create an annotation processor that creates a method called getValue in the class that is annotated. For this I created the following class:
package ro.Gabriel....
0
votes
0
answers
88
views
Does getOpaque/order_relaxed/read_once have influence on the processor, or just the compiler during memory hoisting?
I've had some discussion with multiple people on this issue, and there are some points that makes the usage of memory ordering fences on load situations somewhat confusing.
The first bullet point ...
- 1,293
0
votes
1
answer
47
views
How to match the microarchitectural values produced in the pipeline with its corresponding architectural instruction?
My goal is to match all pipeline values (all the signals at the microarchitectural states in the processor) produced by the execution of the corresonding instruction for a scalar, in-oder RISCV ...
- 37
0
votes
0
answers
62
views
Do modern JIT compilers keep Program Order(PO) inside spinning loops?
The consensus around here seems to be that the famous example given in the "Java Concurrency in Practice" book:
public class NoVisibility {
private static boolean ready;
private ...
- 1,293
-1
votes
1
answer
319
views
AWS EC2 instance crashing whenever I run my python program
I have a Python program for Data Collection from various sources, and then storing the data to my AWS Database using python.
I have developed the code using Python 3.8.
The code runs perfectly on my ...
0
votes
1
answer
186
views
try add a criteria with include for telemetry processor in ApplicationInsights V3 (java) Codeless Approach is not working?
I have to add a new attribute facility on all logs with a filter to name attributes with value toto value, but I don't know why it s not working
maybe including criteria is not working?
I use this ...
0
votes
0
answers
19
views
how to implement this logic in mips [duplicate]
a='Z'
if ('A'<a<'Z'):
print(a.lower())
blt and bgt cant do both of them at the same time because once the condition is met for blt it will branch no matter what of the other condition
blt $t0,'...
0
votes
1
answer
586
views
Should I align data to their data type or cpu cache line size?
Data is usually aligned with its own data type, i.e a 32-bit int is usually aligned to 4 bytes, this makes loading/storing them more efficient for the processor.
Now when does cache line alignment ...
- 2,866
0
votes
0
answers
75
views
How to write bootloader for multi cores ARM cortex-M0 processor
The cores are categorized into one IO-control core, one
DSP core and two normal cores. I managed to find SWD pins but I'm not sure what software to boot, or do I have to create assembly codes? One ...
0
votes
1
answer
86
views
PHP : Filter out text from HTML tags, process it and again place the text where it was (Drupal 9) [duplicate]
I have been trying to find a way to tackle below problem using PHP,
I have a HTML text from CKEditor, I want to replace certain words that I find match with, from a file and add a link to those words. ...
- 4,948
0
votes
1
answer
130
views
Does CryptGenRandom use the RNG in my processor?
On Windows, CryptGenRandom is the standard random number generator to use.
It is called by many packages like Python’s Random and Secrets modules, which both use os.urandom, which in turns calls ...
- 168
0
votes
1
answer
453
views
Why is Pipelined Processor identified as a SISD?
I'm studying pipelined processor and i noticed that a pipelined processor (single core processor) is identified as a Single instruction - single data (flynn taxonomy). I was wondering why?
As a ...
- 421
-1
votes
1
answer
144
views
I can't get the addition and subtraction to execute correctly and the results I'm getting are wrog. How can I fix this?
So I'm trying to desgin a Processor for a university project and as I was going back to check my code I found out that my ALU unit doens't produce the correct results for addition and subtraction. Can ...
2
votes
0
answers
217
views
Mali gpu directory
I cannot find the gpu directory for Mali Gpu's current frequency in the root flile system.
Like in case of Qualcomm Adreno GPU the path for the gpu frequency is /sys/devices/platform/kgsl-3d0.0/kgsl/...
0
votes
0
answers
39
views
Get high utilization CPU% + what service/process is causing it
I would like to know what service that is causing the high CPU utilization into the exisitng code below.
the code works well and sends noticication to me but i just need to add what process or service ...
- 11
0
votes
0
answers
75
views
Reserve a part of memory
Currently I am making some code for a Nordic nRF chip. I want to make it power efficient so I am experimenting with it. A part of that is turning memory sections off. So my goal is to power one block ...
0
votes
0
answers
117
views
Need Help Understanding True/False Statements in Computer Architecture
I am currently studying computer architecture and I am having difficulty understanding the following true/false statements. I would greatly appreciate it if anyone could provide clarification on these ...
- 11
0
votes
0
answers
102
views
Understanding Set Field Value, Tag Field Value, and Cache Hits/Misses in MIPS Processor
I am currently studying computer architecture and I am struggling with a specific exercise involving a 32-bit MIPS processor. The exercise asks to determine the set field value, tag field value, and ...
- 11
0
votes
0
answers
166
views
Understanding the Impact of a MIPS Program on a Direct Mapped Data Cache
I am trying to understand the behavior of a direct mapped data cache in a MIPS processor. I have been given a program and asked to determine which sets of the cache have been updated after the program ...
- 129
0
votes
1
answer
168
views
How does BIOS (generally) change settings on the processor?
I want to confirm my understanding of how BIOS (generally) works such that I can emulate some of the actions it takes without using the kernel driver / userspace library. My goals are purely academic ...
- 1,733
0
votes
0
answers
186
views
How does an ARM processor know when to restore CPSR from SPSR?
I'm currently trying to emulate ARMv4T and wasn't able to find any information about this:
When and exception handler returns, it has to move the saved PC value (r14) to the PC register and set the ...
1
vote
1
answer
129
views
Is port blocked when data is fetching from cache or memory in CPU microarchitecture?
There are two identical memory read ports (port 2 and 3) and one write port (port 4) of Intel Skylake cores. Assuming there are two load instructions issued to port 2 and port 3 parallelly:
When both ...
- 115
0
votes
1
answer
264
views
How to run QEMU with Fedora + Custom kernel
I am trying to run Fedora with QEMU, but with a custom kernel that i built by using the first steps from the readme.txt file from here. The kernel describes T-HEAD's C910 processor, and I want it in ...
- 103
1
vote
1
answer
752
views
What is the difference between processor cores and SMP cores?
In figure 3.2 in the book Distributed Systems: fun and profit, it is mentioned:
Performance advantage of a cluster built with high-end server nodes (128 core SMP) over a cluster with the same number ...
- 4,532
0
votes
1
answer
24
views
manipulation of processor speed without changing the processor
is it possible to replace a ram with higher storage on a machine with a processor of low speed? is speed of processing increased or decreased.
i want to replace the ram drive of my machine with a ...
1
vote
2
answers
449
views
Does a large Max Degree Of Parallelism cause queuing?
I would like to know if my understanding of setting a Max Degree Of Parallelism (MDOP) value larger than a machines available processor amount causes a queueing effect that I have described below.
...
-1
votes
1
answer
182
views
Creating a Processor
It is my last semester but one in university, the sublect is called Architecture and Programming of Microprocessors, the professor wrote this code and i just cannot understand what he is doing. ...
0
votes
1
answer
260
views
Word Addressing in a Single Processor Cache
I've recently come across this description of a single processor cache saying that it's
"Word addressed (addresses are left shifted by 2 by adding “00” to end of address inside the processor, ...
3
votes
2
answers
1k
views
MSR vs MMIO/PCIe configuration space
Intel sometimes uses MSRs and sometimes "internal" PCIe devices to expose configuration options to the OS. I could not find any ressources which describe the advantages/reasons for using ...
3
votes
1
answer
182
views
How to view branch predictor tables of a process using a debugger (gdb)?
I know that most modern processors maintain a branch prediction table (BPT). I have read the gdb documentation but I could not found any command that should give desired results. Based on this, I have ...
- 312
-1
votes
1
answer
63
views
Test and Verification for Designed Softcore Chip
I aim to design an 8-bit softcore processor that can be implemented on the Zedboard Zynq-7000 FPGA. What do you think I should do for validation, test and verification (what kind of testbench or ...
- 1
0
votes
1
answer
391
views
How do processor cores share/run queued threads?
I have a processor with two cores c1 and c2. I have seven threads t0, t1, t2, t3, t4, t5 and t6. t0 is the main thread.
From t0 I create t1 and t2 to handle certain tasks from data d0 obtained from t0....
- 881
0
votes
0
answers
147
views
Apache NIFI - Creating Loop with
sales_order
item_code
description
100
1
Item 1
100
2
item 2
100
3
Item 3
100
4
Item 4
I receive a sales order list in this format and I need to register it in two tables, one for sales order and ...
0
votes
0
answers
799
views
How to Use 100% intel core i9 CPU with Visual Studio 2019?
I have tested with Ryzen 5900X, Visual Studio uses 100% processing and compiles my Source code in 103 seconds. But on another PC with intel core i9 12900K processor, it takes 228 seconds to compile, ...
- 1,136
0
votes
1
answer
3k
views
NPM install maven build failure
I am trying to build an Angular JS project using 'mvn clean install' command. The 'npm install' execution specified in pom.xml is as follows:
<execution>
<id>npm install</id>
<...
- 1
0
votes
0
answers
421
views
Terraform dynamic block module
I am trying to create dynamic block for the below datadog custom pipeline however I can see only verbose category but not Debug category, is there any way to get both debug & Verbose.
Resource:
...
0
votes
1
answer
248
views
What are ps and delta values in Modelsim Verilog?
I am new to Modelsim. I have a processor. In this module clock cycle is 40 ps and I simulate the project with 20 ps speed.
forever #20 clk=~clk;
I have added some variables to the list to be able to ...
- 101
0
votes
1
answer
47
views
If a CPU's stack is 1MB and a programming language is purely pass by value, how can we pass data bigger than 1MB into functions? What happens exactly?
So I hear that using pass by value, copies of the parameters are added to the call stack. Apparently, the stack size on Windows is often 1MB. Obviously though, we can easily pass around data that is ...
