4,600 questions
0
votes
2
answers
39
views
Conditionally updating a target in a Makefile
I have a tool that I use to generate C++ header files as part of the build. I only want to write out the generated headers if they changed from what is already on disk so that I don't trigger a ...
- 1
0
votes
3
answers
43
views
With gnu make, how do you create new source files in the makefile and dynamically add them to compile/link dependency lists?
With gnu make 3.82 how can I get the files created dynamically within a makefile added to a dependencies variable so they get included in the compile & link rules?
If I start off with the ...
- 1
0
votes
0
answers
74
views
Compiling Qt 5.15.15: error: 'XKB_KEY_dead_lowline' was not declared in this scope
I am trying to compile Qt 5.15.15 from scratch because Qt now requires you to create an account in their website.
I've run:
mkdir build
cd build
../configure
gmake
I am getting the following error:
/...
- 13
1
vote
1
answer
43
views
Does makefile .PHONY apply to the target alias names?
Consider the Makefile below, the command clean is declared as PHONY and has an alternative name c.
Does the PHONY attribute apply also to make c or just to make clean?
.PHONY: clean
clean c:
rm -rf ...
- 107
0
votes
1
answer
47
views
MINGW32-MAKE: *** No rule to make target '*.cpp.o', needed by 'module.dll'. Stop
I am trying to compile both C and C++ files into a DLL using a makefile but whenever I build I get the error MINGW32-MAKE: *** No rule to make target 'vendor\whatever*.cpp.o', needed by 'module.dll'. ...
0
votes
1
answer
56
views
Makefile: condition on specific target
In my ideal solution, I want a Makefile that set sanitizers based on SAN variable, only when I call the target "debug", and take care that, as now, gcc do not support -fsanitize=memory, so ...
- 354
1
vote
1
answer
54
views
Multiple make Rules without targets or prerequisites
I might have the terminology wrong so feel free to correct me. We have been abusing make for sometime to do a lot of our builds. 99% of the time this is using phony targets. We have docker build ...
- 14.2k
0
votes
2
answers
59
views
In gnu make how subst works?
Please explain to me what this line of make does(the subst part)?
TRACK_CFLAGS = $(CC):$(subst ','\'',$(ALL_CFLAGS)):$(USE_GETTEXT_SCHEME)
I think it should replace single quote character with \'.
- 542
0
votes
3
answers
42
views
Makefile having a "hidden file" as the NAME target, like .test7?
This is my Makefile:
# the issue seems to be the "." in the filename, since
# if NAME = test7 the desired result is achieved!
# although, when I check the [4.9 Special Built-in Target Names][...
- 37
0
votes
1
answer
20
views
Retrieving the return value of a Python function
I have a Python script, and I want to be able to call one of its functions, which takes a single argument and returns a string, from a Makefile.
I tried the following:
define get_function_ret_value
...
- 13
0
votes
1
answer
43
views
Makefile error when including dependency file
I am adding dependency file support to a Makefile project. I have successfully used dependency file data in previous makefile projects, but this time make is reporting an error I have never seen ...
- 2,460
0
votes
2
answers
57
views
make gives gcc: Permission denied - Error 127
I am executing make.
At some point it enters src and from there it tries compiling sources in several subdirectories.
It gives
gcc -x c++ -ggdb -ansi -pedantic -iquote/home/user1/code -Wall -Wcast-...
0
votes
0
answers
33
views
How to control the background process in scripts run through make?
I have a Makefile with the following content:
MAKEFLAGS += -s
SHELL := /bin/bash
all:
$(MAKE) step1
$(MAKE) -j 2 step2 step3
$(MAKE) step4
step1:
$(MAKE) step1_execute
step1_execute:...
- 13
1
vote
1
answer
44
views
GNU Make: plain dashes are sometimes suppressed in multi-line variables
I'm trying to define with GNU Make v4.4.1 a multi-line variable for a YAML file header, like:
#foo
---
The idea is to echo the header to a file inside a recipe. For a reason unknown to me, the dashes ...
- 496
1
vote
1
answer
47
views
Why does my for-loop in dynamic goal not work?
I'm using GNU Make 3.82 and I want to dynamically create goals in a Makefile using define.
However there was a problem when trying to process the lists passed to the macro. Here is a simple example of ...
- 13
0
votes
2
answers
104
views
Makefile - how to check for the existence of a file from within a rule?
Here is a snapshot fragment of the Makefile logic problem, extremely simplified:
Directory and file structure:
\--project
|---Makefile
\---sub-project
|---Makefile
Contents of /...
- 37
0
votes
2
answers
43
views
Recursive calls to make with $(MAKE) are ignoring my bash script
I have defined my own wrapper of make by using an script that includes a call to time in front of each invocation of make (updating the PATH so bash finds my make first, etc). The script looks like:
#!...
- 12.2k
2
votes
2
answers
67
views
How to include/eval a command output in GNU Make?
Consider that a piece of GNU Makefile is generated by a command (probably because the list of variables to define is too complicated to achieve otherwise).
Script test.sh:
echo 'V1 = foo bar'
echo 'V2 ...
- 661
0
votes
1
answer
55
views
Debugging makefiles with overriden arguments
I'm trying to understand the following target and why it's done this way:
Top-level makefile and target:
collect:
file_list="file_list.txt"
for makefile in $(ALL_PROJECTS) ; do \
...
- 13
0
votes
1
answer
34
views
How should I invoke recursive make across ssh into a local vm?
Typically, I recurse normally:
recipe-X:
$(MAKE) recipe-Y
However, on MacOS I recurse differently:
recipe-X:
ifeq ($(shell uname -s),Darwin)
colima ssh -- make $@
else
<recipe script>
...
- 31k
0
votes
1
answer
33
views
How to stop final rm call when using recursive make [duplicate]
I have a C project that uses gnu make for the build script.
It has the source code split up into modules that are supposed to produce an object archive (.a) file and a header file.
So the directory ...
1
vote
2
answers
61
views
How to overload Makefile rules?
I have a list of header files which I want to compile at once using Makefile. Some of them, however, have an externally defined function in assembly. If that is the case, there is a file with the same ...
- 323
0
votes
2
answers
35
views
What is a [or the proper] make directive to substitute a "/" with a "\" in a makefile path?
I'm trying to write a makefile that will accomidate both a Windows or a Linux based build.
The "/" vs "" is getting in my way. I'm trying to do a character substitution in the ...
- 17
0
votes
1
answer
32
views
GNU make: avoid rules to be executed when files exist already
I have the following make file snippet:
DATA_DIR ?= cpp/gen_data_cpp/build
TXT_FILES := $(wildcard ${DATA_DIR}/*.txt)
BIFI_FILES := $(TXT_FILES:.txt=.txtbifikreversed)
${BIFI_FILES}: ${TXT_FILES} cpp/...
- 751
1
vote
1
answer
34
views
Variable assignment in gmake seems broken?
I know this must be something that I'm doing wrong, but I'm lost.
I have a makefile with a portion that looks like
COMMON_CFLAGS = $(DMFLAGS) \
-I$(subst ;, -I,$(DRV_INCLUDE_LIST)) \
-I$(subst ;, -I,$(...
- 4,546
0
votes
1
answer
37
views
Makefile: Generate rules from a pair of variables
I have a Makefile which has two variables:
SOURCE_DIR := ./source
BUILD_DIR := ./build
C_FILES := $(shell find $(SOURCE_DIR) -name '*.c')
BIN_FILES := $(patsubst $(SOURCE_DIR)%.c,$(BUILD_DIR)%, $(...
- 23
1
vote
1
answer
61
views
Build make target when directory structure changes
I have a script dir.ts that is part of my project website. It generates a JSON file with git repo tree structure, but it takes few seconds to run. Is there a way to check if the directory tree changes?...
- 66.3k
1
vote
0
answers
22
views
gnu make -n behaves oddly for &: targets
I have a makefile where I'm trying to build multiple targets in a single rule. I'm using the new grouped targets feature in GNU Make 4.3.
Here's my sample makefile:
obj1 &: source
touch $@
...
- 13.7k
0
votes
0
answers
42
views
Why Code coverage is not constant during every run?
We have observed that while running code coverage on some open source code (example: openssl-3.0.0-alpha6, postgresql-9.3.6) results in code coverage difference every time.
What will be the possible ...
0
votes
1
answer
87
views
How to tell GNU linker to only try to find unresolved symbol so far from a specific static library?
I added some symbols into a existing src file, this src file is used by both the main program and an independent library. The added symbols belong to the main program hence locate in a static library ...
- 453
1
vote
0
answers
64
views
Unable to run make protoc grpc_php_plugin when create clients in PHP for gRPC services
I'm trying to generating a zeebe-php client stub while referring to this documentation.
I manage to run these command succeffuly:-
$ cd grpc $ mkdir -p cmake/build $ pushd cmake/build $ cmake ../..
...
- 11
0
votes
0
answers
33
views
Pattern rules in makefiles not matched
I have this simple makefile in makefiles/test.mk:
OUT_FLD = out
target: $(OUT_FLD)/target/.wit_target
$(OUT_FLD)/%/.wit_%:
echo "Creating target: $*"
touch $@
.PHONY: target
but ...
- 3,108
0
votes
1
answer
588
views
GNU Make in Ubuntu giving fatal error: rpc/types.h: No such file or directory
I am trying to compile Rockstar (https://bitbucket.org/gfcstanford/rockstar/src/main/).
Compiling with make, I am getting the following error and warnings:
$ make
make[1]: Entering directory '/home/...
- 245
-1
votes
2
answers
74
views
How to pass shell variable returned from pythonscript into another shell to run another pythonscript in Makefile rule?
I am trying for several hours and researched how to pass a shell variable which is returned from a pythonscript into another shellscript to run another pythonscript.
I have an example below:
MyRule:
...
- 69
0
votes
1
answer
190
views
Jumping through hoops to install Sage math: is there a better way?
I need to install Sage for Python on my Windows 10 machine. This has proven more messy than I would hope; I am punished for not using Linux. My specific question is how to get GNU make's build_w32.bat ...
- 353
0
votes
1
answer
41
views
Order only prerequisite not executed by make
I have a rule adddefs.h that needs to be executed before the compiling and linking rules. So I have defined this rule as an order only prerequisite.
........................................
.PHONY: ...
- 795
-1
votes
1
answer
33
views
When build glibc, it has err "No rule to make target '/home/roroco/Dropbox/cpp/cpp-global-deps/glibc-glibc-2.28/build/assert/stamp.os'"
echo "/home/roroco/Dropbox/cpp/cpp-global-deps/glibc-glibc-2.28/dist/lib " \
| gawk -f gen-trusted-dirs.awk > /home/roroco/Dropbox/cpp/cpp-global-deps/glibc-glibc-2.28/build/elf/...
- 4,107
1
vote
2
answers
73
views
How to create a make-target which is an implicit dependency for all other targets?
I know .PHONY targets which will be executed every time a target depends on them:
.PHONY: preparation
preparation:
@echo "Do something that has to be done before every other target"
...
- 9,708
0
votes
0
answers
55
views
The multi-task parallel mechanism of ”MAKE -j“ seems not to be working in a server environment
When I compile around 1700 files using make -j, it takes 13 minutes on an 8-core PC with 100% CPU load, whereas on a 56-core server, it takes 7 minutes but with only 10% CPU load.
Use MINGW64, ...
- 33
0
votes
3
answers
52
views
How to find the prerequisite from list based on target list
GNU Make 3.80 on Windows 11
I have a list of files and a list of destinations. I need to write a rule that will copy each file to its corresponding destination (in a specified subdirectory). Note, ...
- 26
0
votes
1
answer
24
views
How to override a included Makefile variable when it is used for dependency list?
I have Makefiles for several custom domain specific languages. One of them require weird paths for the input/output files passed to the compiler, So I had to use some gnumake tricks. Now they are not ...
- 14.7k
0
votes
1
answer
47
views
Makefile: implicit rule with sub dirs
How to write an implicit rule to cover all sources in a sub directory with more sub directories and build objects in the current directory? Here is an example:
rootdir
├─ src
│ ├─ main.c
│ └─ sub
│ ...
- 353
0
votes
2
answers
74
views
Post-target in Makefile
I have a Makefile with several targets, and I want to automatically run a target named collect-data-point after any target is called. I'm trying to figure out how to add this post-target execution ...
- 87
0
votes
0
answers
47
views
String replacement in makefile
I have a small snippet to replace kvvm60 to main in a directory path where it's not working as expected.
hello:= /home/kvvm60/foo/bar
$(info inside hello $(hello))
TEST := $(patsubst %kvvm60%,%main%,...
- 37
1
vote
1
answer
49
views
Define make rule to modify make variable
I'm trying to define a make rule that modifies a make variable, as a way to conditionally compile the code.
Something like:
[...]
LD_PREL:=
all: main
main: $(OBJ)
$(COMP) $(DEBUG) $(FLAGS) $^ -...
- 375
0
votes
1
answer
65
views
Run a rule but allow intervention
I'm writing a makefile.
I have an artifact data and I use gpt to process it. Due to token limits, I have to break the data into segments (rule segments), each processed by AI (rule ai), then assemble ...
0
votes
2
answers
53
views
GNU make: how to count the up-to-date targets?
I'd like to display a progress bar during building with GNU make. It works great for clean builds, but it's inaccurate for incremental builds.
To calculate the actual progress, we need to know the ...
- 925
0
votes
1
answer
38
views
GNUMake: How to use patterns with subdirectories?
My original Makefile build rules were:
SRCS := $(shell find . -name '*.c')
HEADERS := $(shell find . -name '*.h')
OBJS := $(SRCS:.c=.o)
%.o : %c
$(CC) -c $(CFLAGS) $< -o $@
executable : $(OBJS) ...
- 1,396
0
votes
1
answer
48
views
make file failing with No such file or directory
I'm running makefile in Githubactions. My makefile is failing to run touch command. I'm not sure what is the error here.
Tried adding : `$(shell) to make command, still the same error. It worked in ...
- 763
0
votes
0
answers
16
views
Is there any cross make/bash variable expansion syntax?
For example, I have a configuration file that I can source from either make or bash:
# mycfg.sh
FOO='bar'
BAR="${FOO}bar"
MYHOST=localhost # local, although will be arbitrary IP in ...
- 31k