I know access to ports in I/O address spaces requires specific IN/OUT instructions and they are not part of Physical memory( RAM) but I have not understood Where is the I/O address space actually located (Physically)? (some sort of RAM in )I/O controller? Reserved side of physical memory?
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the physical hardware will be all over the place. e.g. the in/out instructions in the cpu themselves, the actual i/o wires in the various sytems busses and chips (northbridge, southbridge), etc..., wherever the hardware providing the ports physically resides.– Marc BCommented Jan 5, 2015 at 18:46
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This question doesn't make sense. I/O ports on x86 do not exist in memory at all. They do not have memory addresses.– user149341Commented Jan 5, 2015 at 19:06
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duskwuff I understand they do not have memory addresses. That is why I am asking where they are located? does CPU access device registers directory? are the registers mapped to somewhere? if mapped where are they mapped? I am trying to understand low level detail of when IO/OUT instructions are executed?– Frank CooolCommented Jan 5, 2015 at 19:53
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Marc, you are close to answering my question. Can you give me an example. Lets say this PCIE endpoint device located at bus 0, How does CPU get the data when executing IN/OUT instruction ( from the PCIE device registers directly) or from PCI controller (registers) or registers located at Southbridge?– Frank CooolCommented Jan 5, 2015 at 19:57
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control signals on the bus determine this, the control signals are ultimately derived from the instruction and the layers between the processor core and the busses. Jasen pretty much covers this, although I think there is I/O space in the pci(e) for legacy reasons although so that the cards work everywhere I would assume that most I/O is memory mapped...It may be that the x86 pcie controllers or somewhere between the core and the controller convert I/O to memory mapped, not sure. easy to google and find out though...– old_timerCommented Jan 5, 2015 at 22:16
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3 Answers
On the early X86 processors (and also the 8080, Z80 etc) I/O address space was on the same data and address bus as the memory, but was accessed by activating a dedicated IO-request pin on the CPU
So electrically I/O was in parallell with the RAM
Thses days the CPU speaks HDMI and PCIe directly so much of the I/O space is either internal to the CPU (eg: the VGA I/O interface) or accessed over th serial bus that is PCIe PCIe is also used for memory mapped I/O so in that respect IO is still accessed over mostly the same electrical interfaces as memory mapped IO . but not over the same IO pins that are used for RAM any more,
A list of I/O addresses can be found in Ralf Browns x86/MSDOS Interrupt List:
http://www.pobox.com/~ralf
http://www.pobox.com/~ralf/files.html
ftp://ftp.cs.cmu.edu/afs/cs.cmu.edu/user/ralf/pub/
inter61d.zip: "PORTS.A", "PORTS.B", "PORTS.C"
answered Jan 6, 2015 at 0:53
First, you should understand that a device can be programmed to respond to any address, even if that address is not part of physical memory. This is done by programming their memory decoders. In short, the memory for I/O devices is located on the device. The I/O space provided to the device usually maps the memory which is on the device, i.e., each I/O device provides it's own memory.
Well, in the old days, there were certain "well-known" addresses, for instance, 0x3f8, 0x2f8 for com (serial) ports, 0xCF8-0xCFC for PCI config space. These addresses do not use any physical memory, a separate I/O signal is asserted to indicate such. These devices memory decoders were programmed at the factory to respond to these addresses only when the I/O pin is asserted.
But this became obsolete. Even in the later days of PCI, most devices were initially configured through IO space, but then their memory decoders were programmed to respond to a memory-mapped address in the virtual space above physical memory. When memory decoders are programmed, not only is the base address provided but also the size of that address space is provided as well to avoid collisions between devices. The memory is located on the device, not in the host computer's RAM or chipset.
For PCI-express, I believe now the acpi table is consulted for the memory-mapped space and i/o instructions are essentially deprecated. Serial ports are not usually included on modern hardware. And even if they were it would be implemented on a PCI or PCIe device.
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I should also add that most PCI devices will also indicated the amount of address space they would like to have, so when software programs the memory decoders they can take this request into account. Commented Jan 6, 2015 at 3:36
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By "memory decoder" you seem to be actually referring to an address decoder. Your assertion that "a device can be programmed to respond to any address" is not always true because the address decoder could be hardwired or only hardware configured.– sawdustCommented Jan 3, 2021 at 0:06