I'm new to verification and system verilog in general. I wanted to know howHow I can use a design input with the repetition operator in a SV assertion.? Basically, what I'm trying to implement is:
property ( ( disable iff((a) or (b) or (c) or (d))
$rose(req) |-> req[*32]
Here I'm trying to replace the 3232
with t_req, which is an input to the design module and can be changed by the user.
Is there any way to make the assertion dynamic so that the value 32 is not hardcoded?