Papers by Darian Reyes Fernadez de Bulnes
Scientific Programming, Jun 29, 2020
Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is... more Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. is process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NPhard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. is paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.
Zenodo (CERN European Organization for Nuclear Research), Jan 8, 2019
Minimum Population Search is a recently developed metaheuristic for optimization of monoobjective... more Minimum Population Search is a recently developed metaheuristic for optimization of monoobjective continuous problems, which has proven to be a very effective optimizing large scale and multi-modal problems. One of its key characteristic is the ability to perform an efficient exploration of large dimensional spaces. We assume that this feature may prove useful when optimizing multi-objective problems, thus this paper presents a study of how it can be adapted to a multi-objective approach. We performed experiments and comparisons with five multi-objective selection processes and we test the effectiveness of Thresheld Convergence on this class of problems. Following this analysis we suggest a Multi-objective variant of the algorithm. The proposed algorithm is compared with multi-objective evolutionary algorithms IBEA, NSGA2 and SPEA2 on several well-known test problems. Subsequently, we present two hybrid approaches with the IBEA and NSGA-II, these hybrids allow to further improve the achieved results.
IEEE Latin America Transactions, Jul 1, 2015
In productive projects supervised with Redmine tool, risks management is not realize with the ent... more In productive projects supervised with Redmine tool, risks management is not realize with the entire rigor required in the project manager inside the tool. Redmine doesn't have incorporated any feasible tool that offers to the project leaders a weapon for combating the uncertainties that may arise in the future. Therefore, it is required the implementation of a tool that provides solutions to these inconveniences. This research has as main objective to develop a plugin application Redmine project manager, able to efficiently automate the quantitative risk analysis. Following this goal was obtained as a result of an extension to the Redmine web application, using Montecarlo simulation, can quantitatively analyze the risks in the software life cycle.
This paper is about the thermal and hydraulic characterization of a compact heat exchanger having... more This paper is about the thermal and hydraulic characterization of a compact heat exchanger having two row of tubes and rectangular wavy fins. The dimension of the tubes and the fin are similar to the used in the air conditioning and refrigeration area. A numerical approach was used and the computational domain was implemented using symmetry and periodic condition. Were considered extended inlet and outlet section for accuracy. The numerical procedure ant its model were certified against published literature and a good match was found. The impinging flow on the fin surface was found responsible for the differences between the heat transferred at every side of the fin. The differences disappearing when the average value was calculated. Key words: wavy fin, compact heat exchanger, numerical model, thermo-hydraulic behavior. ________________________________________________________________________________ Resumen Este trabajo trata sobre la caracterizacion termica e hidraulica de un inte...
Computación y Sistemas, 2018
En problemas de optimización multi-objetivo, se plantean dos o más funciones objetivo que se opti... more En problemas de optimización multi-objetivo, se plantean dos o más funciones objetivo que se optimizarán al mismo tiempo, buscando el conjunto de las mejores soluciones de compromiso, o conjunto Pareto. Este es el caso de la ingeniería de tráfico multicast, que pretende optimizar costo y retardo entre otras posibles métricas. Como han sido publicados numerosos Algoritmos Evolutivos Multiobjetivos o MOEAs, no queda aún claro cual es el que presenta mejor desempeño para el problema considerado. Por esta razón, en este trabajo hacemos una comparación experimental entre 5 alternativas: NSGA, NSGA2, SPEA, SPEA2 y cNSGA2, con el fin de determinar cual es la más apropiada para resolver problemas de enrutamiento multicast. Resultados experimentales demuestran que algoritmos como el SPEA y SPEA2 logran un excelente desempeño en este tipo de problemas.
2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), 2016
Operation scheduling is a fundamental problem in mapping an application to electronic devices. In... more Operation scheduling is a fundamental problem in mapping an application to electronic devices. In scenarios where these schedules are made on Data Flow Graph (DFG), it is necessary to convert the result to Hardware Description Language (HDL) code. We present a detailed approach for generate VHDL code described in a Data Flow Graph (DFG). We generate VHDL code corresponding to Moore Finite State Machine (FSM), because is similar with the logic of the DFG. We use 20 DFGs from benchmark Mediabench to compute different experiments and we report the occupied area (Slice registers and LUTs) of VHDL codes on a FPGA device. We expose conversions made from DFG scheduling and mapping with As Soon As Possible (ASAP), As Late As Possible (ALAP) and Random scheduling algorithms. All codes are simulated with Xilinx ISE Design Suite to demonstrate its validity.
Computación y Sistemas, Thematic Issue on Numerical and Evolutionary Optimization, 2018
Operations scheduling is a fundamental problem of mapping a design into an electronic device, suc... more Operations scheduling is a fundamental problem of mapping a design into an electronic device, such as a Field Programmable Gate Array (FPGA). In this paper, a proposal for apply the multi-objective evolutionary algorithms, such as, NSGA-II, SPEA2 and NSGA-III for the simultaneous optimization of area, delay and power in the in high-level synthesis stage in the FPGAs is presented. Results obtained are compared using the quality indicators, Epsilon, Hypervolume and R, these results shown which of the algorithms are the most suitable for this problem to solve. Then, the results of the evolutionary processes are analyzed and improvements are proposed.
Operations scheduling and Lookup Table (LUT) based technology mapping are fundamental problems of... more Operations scheduling and Lookup Table (LUT) based technology mapping are fundamental problems of mapping designs onto an electronic device, such as a Field Programmable Gate Array. We present an approach to apply two optimizations consecutively. As first optimization, we apply several metaheuristic algorithms for multi-objective optimization at the High-Level Synthesis stage. As a second optimization, we realize reductions of LUTs at the Logic Synthesis stage. Several circuit designs are represented in a Data Flow Graph (DFG) and the experiments are carried out on the standard Mediabench benchmark. In the first optimization, we compared NSGA-II, FEMO, HypE, IBEA, SPEA2 and WSGA. Results have an average improvement 14.06% in occupied Area and 7.01% in Power consumption. Then, optimized DFG schedules are converted into Very High Description Language code using the Xilinx ISE Design Suite tool. Later, in the second optimization, The IMap algorithm is used to obtain combinational area reductions. Results show that 60% of the circuits are improved in comparison with the Xilinx ISE Design Suite.
Fuzzy logic compared to conventional logic can work with imprecise information to define conventi... more Fuzzy logic compared to conventional logic can work with imprecise information to define conventional assessments, contrary to conventional logic that allows working with defined and precise information. In this paper proposes to implement a fuzzy system in the ELVIS-FPGA board, with novel methodologies for the fuzzification stage. Comparisons are made of fuzzy system proposed versus fuzzy system using toolbox of LabView(without FPGA), the results are similar to those obtained by said toolbox. Resumen: La lógica difusa en comparación con la lógica tradicional puede trabajar con información imprecisa para definir evaluaciones convencionales, contrario con la lógica tradicional, la cual permite trabajar con información precisa. Este artículo propone implementar un sistema difuso en la tarjeta ELVIS-FPGA, con novedosas metodologías para la etapa de fuzzificación. Se llevaron a cabo comparaciones del sistema difuso propuesto contra el sistema difuso diseñado en la caja de herramientas d...
This paper is about the thermal and hydraulic characterization of a compact heat exchanger having... more This paper is about the thermal and hydraulic characterization of a compact heat exchanger having two row of tubes and rectangular wavy fins. The dimension of the tubes and the fin are similar to the used in the air conditioning and refrigeration area. A numerical approach was used and the computational domain was implemented using symmetry and periodic condition. Were considered extended inlet and outlet section for accuracy. The numerical procedure ant its model were certified against published literature and a good match was found. The impinging flow on the fin surface was found responsible for the differences between the heat transferred at every side of the fin. The differences disappearing when the average value was calculated. Resumen Este trabajo trata sobre la caracterización térmica e hidráulica de un intercambiador de calor compacto con dos filas de tubos circulares y aletas onduladas rectangulares. Las dimensiones de los tubos y las aletas son similares a las usadas en el área de la climatización y la refrigeración. Se utilizó un abordaje numérico y el dominio computacional implementado se completó con condiciones de contorno de tipos simétrica y periódica. El dominio fue extendido en ambas direcciones del flujo para aumentar la precisión de los resultados. El procedimiento numérico y el modelo implementado fueron validados frente a valores publicados en la literatura con los cuales se obtuvo un buen ajuste. La incidencia del flujo sobre la superficie de la aleta fue encontrada responsable por las diferencias encontradas entre el comportamiento de ambos lados de la aleta. Las diferencias encontradas desaparecen cuando se considera el calor total transferido por la aleta. Palabras claves: aleta ondulada, intercambiador de calor compacto, desempeño termo-hidraulico Introducción Extended surface or fins are employed frequently to augment the heat transferred from tubes in heat exchangers. Every fin has its own design and many differences can be found when they are compared. The plate fin is the simplest and is considered the basic configuration. Prediction of pressure drop and heat transferred by a fin-tube heat exchanger constitute a hard and many times an expensive task. This is because exist a complex flow pattern when it is flowing through a heat exchanger channel between consecutive fins. Every modification of the basic geometry need to be investigated as a new one to obtain its thermal-hydraulic performance. Several models of wavy fins can be created only by modification of its main dimensions. The transversal and longitudinal pitches, tube diameter, fin spacing and angle of the wavy are magnitudes which determine the thermal performance and the pressure drop of a heat exchanger consist of tubes and wavy fins. In 1996 Wang et al [1] carried out a study of convex louver fins and it was compared with, among others, a wavy fin. The Reynolds number based in the collar diameter ranged from 400 to 8000. This work had an experimental approach and the wavy fin studied had 25,4 mm and 1,05 mm as transversal and longitudinal pitches respectively. The model had two row of tubes and a fin pitch of 2,54 mm. The collar diameter was 10,06 mm. The pressure drop of the wavy fin was found comparable to the pressure drop of the others fins and higher than pressure drop of the plate fin. On the other hand, the heat transfer data were presented as a multiplication of the fin efficacy by the average heat transfer coefficient (0 xh η). The importance of this article is the experimental data presented, which can be used as a reference for validations. An extensive work of Wang et al [2] was dedicated just to wavy fin. Two different configuration of wavy fin were considered. The fin pitch was varied and its effect on the heat transfer was analyzed. Was found a negligible effect of the fin edge corrugation in the studied geometries. An important result was the correlation, proposed for j and f and valid for the studied geometries. The general dimensions of this geometries were bigger than used in this work.
In productive projects supervised with Redmine tool, risks management is not realize with the ent... more In productive projects supervised with Redmine tool, risks management is not realize with the entire rigor required in the project manager inside the tool. Redmine doesn't have incorporated any feasible tool that offers to the project leaders a weapon for combating the uncertainties that may arise in the future. Therefore, it is required the implementation of a tool that provides solutions to these inconveniences.This research has as main objective to develop a plugin application Redmine project manager, able to efficiently automate the quantitative risk analysis.Following this goal was obtained as a result of an extension to the Redmine web application, using Montecarlo simulation, can quantitatively analyze the risks in the software life cycle.
Conference Presentations by Darian Reyes Fernadez de Bulnes
Numerical and Evolutionary Optimization Workshop (NEO 2018), 2018
The Field Programmable Gate Array (FPGA) has become increasingly popular in different areas of kn... more The Field Programmable Gate Array (FPGA) has become increasingly popular in different areas of knowledge. High-Level Synthesis (HLS), also known as Behavioral Synthesis, is the process of transform algo-rithmic description to synthesizable Register Transfer Level (RTL) netlist into electronic devices such as FPGAs. HLS allows designers to work at a higher-level of abstraction by using a software to define the hardware behavior. Inside this process, there are several opportunities to perform optimizations during the scheduling, allocation, and binding of a circuit design. The scheduling defines how all design's operations will be scheduled into clock cycles. The allocation determines the type and the number of hardware resources (for instance: functional units, storage, or connectivity components) needed to satisfy the design's constraints. The binding determines how each variable (carried out values across clock cycles) will be bound to a storage unit [2]. These optimizations are highly multi-objective by nature, with compromise between objective functions, such as, delay, area, and power [1]. For the optimization of several objective functions at the same time, it is necessary to apply Multi-Objective Evolutionary Algorithms (MOEAs). In the last ten years, several efforts have been made to create software tools for HLS containing multi-objective optimizations [3]. However, those proposals have many limitations, mainly because they focus on being an Electronic Design Automation (EDA) tool, and not in the performance of the optimization. Some of these limitations are: a bit possibility in the variation of the multiobjective optimization algorithm and its parameters, lack of charts about the optimization process to find details of interest, no access to the Pareto Front in order to the designer can choose which solution is going to implement in an FPGA, and that the optimization process is executed on the user side, instead of in an online server with high potential for computing and parallelization. To overcome these limitations, we are developing VHDL by MOEA, an academic software approach to apply MOEAs for simultaneous minimization of delay, area, and power during HLS process. VHDL by MOEA has as input a VHDL code with the behavioral description to be implemented. As output, the optimized VHDL code is obtained. To achieve this, the software has four general modules that communicate with each other. In the first module the compile task is done, the input VHDL code is syntactically validated and it is converted to Data Flow Graph (DFG) using the libraries Flex and Bison. The second one is capable of performing the multi-objective optimization on the DFG with the MOEAs NSGA-II, NSGA-III and SPEA2 with a multi-chromosome representation. The third module converts the optimized DFG in RTL written in VHDL code, this output VHDL code is a Finite State Machine design and it is ready to be implemented into the FPGA device with an EDA tool like a Vivado by Xilinx. The function of the fourth module is controlling the three previous modules and create an automated process for the designer. This last module is web-based with a Model-View-Controller architecture. The first three modules are written in C++ language and the fourth one in Python. MySQL database is used and data exchange is
Numerical and Evolutionary Optimization Workshop (NEO 2017), 2017
The Field Programmable Gate Array (FPGA) is a semiconductor device containing logic blocks whose ... more The Field Programmable Gate Array (FPGA) is a semiconductor device containing logic blocks whose in-terconnection and functionality can be congured in situ. Operations scheduling is a fundamental problem of mapping a design into an electronic device, such as a FPGA. High-Level Synthesis (HLS), also known as Behavioral Synthesis, is the process of transform algorithmic description to synthesizable Register Transfer Level (RTL) netlist in FPGA devices. When the objective functions are said to be conicting, and there exists a number of Pareto optimal solutions the problem is multi-objective. In this paper, the optimization of HLS is a multi-objective problem because three objectives such as area, power and delay are mutually conicting. We present an approach to apply Multi-Objective Evolutionary Algorithms (MOEAs) for simultaneous optimization of area, delay and power during HLS process. The technique performs scheduling and allocation of functional units and registers concurrently. RTL netlist can be depicted using Data Flow Graphs (DFGs). A DFG represents an operation set that must run sequentially or in parallel to achieve the results. Each graph node is a contiguous code region and the edges are arithmetic operations, such as addition, multiplication or logical function. MOEAs procedure is a population-based stochastic search which iteratively emphasizes its better population members. The solution for multi-objective optimization problem is not a single solution as for mono-objective optimization problem, also is a set of solutions dened as Pareto Front (PF). A solution of PF is optimal if it is not possible to improve an objective without deteriorating the other objective. Solutions sets represent the compromise between the dierent objectives. In this propose, a chromosome has a node scheduling priority eld and a module allocation eld. The chromosome is a simultaneous scheduling of a DFG and functional unit allocation can be carried out. The DFG nodes are scheduled using a list scheduling heuristic. We perform experiments applying NSGA-II, SPEA2 and NSGA-III algorithms for this combinatorial problem. For the experiments, PISA framework is used. This platform is based on separating the optimization process in two parts: the optimization problem and the selection process. Results are analyzed using the quality indicators: Epsilon, Hypervolume and R. Quality indicator measure convergence to the optimal PF and diversity of solutions of the PF. Experiments are performed on a standard benchmark named Mediabench. Thereafter, we discuss which MOEA has a better behavior based on convergence and diversity. The main contribution of this work is the MOEAs comparison for area, delay and power optimization during HLS process in FPGA devices. In addition, the evolutionary process is analyzed and some weaknesses were discovered within the generations of the MOEAs.
Fuzzy logic compared to conventional logic can work with imprecise information to define conventi... more Fuzzy logic compared to conventional logic can work with imprecise information to define conventional assessments, contrary to conventional logic that allows working with defined and precise information. In this paper proposes to implement a fuzzy system in the ELVIS-FPGA board, with novel methodologies for the fuzzification stage. Comparisons are made of fuzzy system proposed versus fuzzy system using toolbox of LabView(without FPGA), the results are similar to those obtained by said toolbox. Resumen: La lógica difusa en comparación con la lógica tradicional puede trabajar con información imprecisa para definir evaluaciones convencionales, contrario con la lógica tradicional, la cual permite trabajar con información precisa. Este artículo propone implementar un sistema difuso en la tarjeta ELVIS-FPGA, con novedosas metodologías para la etapa de fuzzificación. Se llevaron a cabo comparaciones del sistema difuso propuesto contra el sistema difuso diseñado en la caja de herramientas de LabView(sin FPGA), los resultados obtenidos son similares a los que se obtienen con la caja de herramientas.
Operation scheduling is a fundamental problem in mapping an application to electronic devices. In... more Operation scheduling is a fundamental problem in mapping an application to electronic devices. In scenarios where these schedules are made on Data Flow Graph (DFG), it is necessary to convert the result to Hardware Description Language (HDL) code. We present a detailed approach for generate VHDL code described in a DFG. We generate VHDL code corresponding to Moore Finite State Machine (FSM), because is similar with the logic of the DFG. We use 20 DFGs from benchmark Mediabench to compute different experiments and we report the occupied area (Slice registers and LUTs) of VHDL codes on a FPGA device. We expose conversions made from DFG scheduling and mapping with As Soon As Possible (ASAP), As Late As Possible (ALAP) and Random scheduling algorithms. All codes are simulated with Xilinx ISE Design Suite to demonstrate its validity.
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Papers by Darian Reyes Fernadez de Bulnes
Conference Presentations by Darian Reyes Fernadez de Bulnes