ACM Transactions on Design Automation of Electronic Systems, 2004
We present a framework for high-level synthesis that enables the designer to explore the best cho... more We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by reordering , speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.
ACM Transactions on Design Automation of Electronic Systems, 2004
We present a framework for high-level synthesis that enables the designer to explore the best cho... more We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by reordering , speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.
Uploads
Papers by rajesh gupta