Papers by khaled hayatleh
Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number o... more Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. V BE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes 51.8μW power from 1V power supply and occupies 2478 μm2 silicon area
Analog Integrated Circuits and Signal Processing, 2022
This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental... more This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180nm CMOS process and operating with ±1.8V supply rails, the input resistance is 1.05ohms and the power dissipation is 93.6µW. The bandwidth, for a gain of 100dBohm, exceeded 9MHz. For a 1µA, 1MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09pA/√Hz and with a photodiode capacitance of 2pF is 8.52pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5pF to 2pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.
2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006
A symmetrical BJT voltage-follower is presented which combines low harmonic distortion and high s... more A symmetrical BJT voltage-follower is presented which combines low harmonic distortion and high slew rate. Unlike conventional class-AB voltage-followers the proposed design provides large signal swing, some plusmn4.5 V on a plusmn5 V power supply, as well as large positive and negative output currents for driving capacitive loads, resulting in high slew-rate capability. The circuit exhibits gain flatness of 0.1 dB at 728 MHz with an inductive behaviour coming in at higher frequencies. The operational range is -20degC to +100degC with a power consumption of 55 mW at room temperature.
… and Computers in …, 2008
This paper presents a novel voltage-follower, implemented in bipolar technology, based on a globa... more This paper presents a novel voltage-follower, implemented in bipolar technology, based on a global feedback technique. The evaluation of the circuit has been carried out using extra fast complimentary transistors and the biasing circuitry followed the same design philosophy. The proposed design exhibits very high input and very low output impedance, due to the feedback technique, for operating frequencies beyond 1GHz. The small-signal bandwidth achieved is higher than 3GHz, the output voltage swing is some ±3.2V, the offset voltage is around 200uV while the input offset current is just above 130nA. The new circuit achieved gain flatness to within 0.1dB up to 170MHz, featuring total harmonic distortion better than-65dB and intermodulation distortion of around-70dB, for capacitive loads up to 10pF. The operation of the novel design is specified from-20 o C to +100 o C and the power dissipation is some 52mW on a ±5V power supply.
Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS te... more Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area
2017 Second International Conference on Electrical, Computer and Communication Technologies (ICECCT), 2017
In this paper a novel CMOS temperature and supply voltage independent current reference has been ... more In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/ 0 C against temperature variation of-40 0 C-120 0 C and line sensitivity of 337ppm/V against supply variation of 0.6-1.8V, while consuming 135uW from 1.8V supply and occupying 5184um2 Keywords-current reference; PTAT; voltage independent; temperature independent; MOS.
2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018
In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitativ... more In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55 0 phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.
2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2020
Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number o... more Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. VBE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes $51.8\mu \mathrm{W}$ power from 1V power supply and occupies $2478\ \mu \mathrm{m}^{2}$ silicon area.
Journal of Circuits, Systems and Computers, 2019
This paper describes a high-performance impedance measurement circuit for the application of skin... more This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have ... more Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have been designed and developed. They are transistor level based designs, ideally suited for ASIC realisation. The two different, architecture circuits are described. In the first design a comparator is used to control a current-steering circuit to achieve the required unipolar output response. The topology of the circuit exhibits high speed performance with minimum transients. The second design is a development from the first. The circuit has lower overall complexity and provides enhanced performance. It is based on an emitter-coupled common-collector, with a NPN Quasi-Darlington dynamic buffer. Both techniques show promising performance in terms of operating speed.
International Journal of Electronics Letters, 2015
This document is the post print version of the journal article. Some differences between the publ... more This document is the post print version of the journal article. Some differences between the published version and this version may remain and you are advised to consult the published version if you wish to cite from it.
Measurement Science and Technology, 2006
ABSTRACT
Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, 2010
The decision for the most appropriate current mirror topology when designing a circuit is a matte... more The decision for the most appropriate current mirror topology when designing a circuit is a matter of trade-offs between impedance, current transfer ratio, area on chip, power consumption and voltageheadroom, expandability etc. Current mirrors are mainly used for biasing, for transferring current from one part of the circuit to another or as load for amplifier stages. This paper presents the theoretical analysis, the simulation and the circuit built of a current mirror with excellent performance characteristics compared to conventional designs at the expense of voltage-headroom. Great emphasis in the analysis of the circuit has been paid on the current transfer ratio and the output impedance of the configuration.
IEEE Transactions on Instrumentation and Measurement, 2011
2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
Low operating power supply is very critical for advanced CMOS technology based circuits. A techni... more Low operating power supply is very critical for advanced CMOS technology based circuits. A technique to reduce the minimum operating Vdd of opamp has been proposed by deploying a source follower based level shifter. Demonstrated the robustness of the proposal in 65nm CMOS technology and simulated with Spectre. Simulation results show that 60dB dc gain and 10MHz bandwidth of the opamp. Compared to the conventional folded cascode opamp, the present proposal makes opamp works up to 0.8V while conventional one fails at 1.3V. Circuit Draws with 205uA from 1.5V supply and occupying 0.002464mm2silicon area.
2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
In this paper, a PVT insensitive variable gain amplifier (VGA) has been proposed which is suitabl... more In this paper, a PVT insensitive variable gain amplifier (VGA) has been proposed which is suitable for bio-medical neural recording. Proposed amplifier delivers an appreciably enhanced performance over that of existing technique. Constant Gm bias stability is described in the frequency domain. Noise problems with the existing technique are described qualitatively. A prototype circuit has been implemented in 65nm CMOS technology and simulated with Spectre. 2–25dB gain programmable range was achieved across PVT and 0.3dB standard deviation. 1.2uV integrated RMS noise was achieved. The circuit consumes 0.5mA from the 1.5V supply voltage and occupies 4500um2 silicon area.
Journal of Circuits, Systems and Computers
This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes th... more This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.
Journal of Circuits, Systems and Computers
This paper describes a technique to detect blood cell levels based on the time-period modulation ... more This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184-[Formula: see text]m2 silicon area and consumes 216[Formula: see text][Formula: see text]A from a 1-V power supply.
SAE Technical Paper Series
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Papers by khaled hayatleh