The paper considers the problem of model checking real-life VHDLbased hardware designs via their ... more The paper considers the problem of model checking real-life VHDLbased hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e., designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.
ABSTRACT To improve throughput of personal computers used as In-ternet routers, hardware accelera... more ABSTRACT To improve throughput of personal computers used as In-ternet routers, hardware acceleration can be used. Packet classification unit employed in the design utilizes content addressable memory com-bined with comparison instructions. Routing, link layer addressing, and packet filtering has to be performed in a single operation. We have de-veloped a representation of the first two called routing-ARP table, and representation of filters based on decision diagrams. In this paper, we describe a method to combine them all together and convert the resulting structure into the hardware device. As a special case, the algorithm converts a decision diagram into a first-match struc-ture. Dealing with implementation and limited hardware resources is mentioned.
We unify a view on three extensions of Process Rewrite Systems (PRS) and compare their expressive... more We unify a view on three extensions of Process Rewrite Systems (PRS) and compare their expressive power with that of PRS. We show that the class of Petri nets is less expressive up to bisimulation equivalence than the class of PA processes extended with a finite state control unit. Further we show our main result that the reachability problem for PRS extended with a so called weak finite state unit is decidable. wPRS r r r r r r r r r r r r r r r r r r r r r r r r K fcPRS r r r r r r r r r r r r r r r r r r r r r r r r K (G, G)-PRS r r r r r r r r r r r r r r r r r r r r r r r K r r r r r r r r r r r r r r r r r r r r r r r r
ABSTRACT We introduce improvements in the algorithm by Gastin and Oddoux translating LTL formulae... more ABSTRACT We introduce improvements in the algorithm by Gastin and Oddoux translating LTL formulae into B\"uchi automata via very weak alternating co-B\"uchi automata and generalized B\"uchi automata. Several improvements are based on specific properties of any formula where each branch of its syntax tree contains at least one eventually operator and at least one always operator. These changes usually result in faster translations and smaller automata. Other improvements reduce non-determinism in the produced automata. In fact, we modified all the steps of the original algorithm and its implementation known as LTL2BA. Experimental results show that our modifications are real improvements. Their implementations within an LTL2BA translation made LTL2BA very competitive with the current version of SPOT, sometimes outperforming it substantially.
This paper presents the verification of CRC algorithm properties. We examine a way of verifying o... more This paper presents the verification of CRC algorithm properties. We examine a way of verifying of a CRC algorithm using exhaustive state space exploration by model checking method. The CRC algorithm is used for calculation of a message hash value and we focus on verification of the property of finding minimal Hamming distance between two messages having the same hash value. We deal with 16, 32 and 64 bits CRC generator polynomials, especially with one used in the Liberouter project. ⋆ This research has been supported by the CESNET activity "Programmable hardware" .
We establish a decidability boundary of the model checking problem for infinitestate systems defi... more We establish a decidability boundary of the model checking problem for infinitestate systems defined by Process Rewrite Systems (PRS) or weakly extended Process Rewrite Systems (wPRS), and properties described by basic fragments of action-based Linear Temporal Logic (LTL) with both future and past operators. It is known that the problem for general LTL properties is decidable for Petri nets and for pushdown processes, while it is undecidable for PA processes. We show that the problem is decidable for wPRS if we consider properties defined by LTL formulae with only modalities strict eventually, strict always, and their past counterparts. Moreover, we show that the problem remains undecidable for PA processes even with respect to the LTL fragment with the only modality until or the fragment with modalities next and infinitely often. 2 L. Bozzelli et al.
We focus on the realizability problem of Message Sequence Graphs (MSG), i.e. the problem whether ... more We focus on the realizability problem of Message Sequence Graphs (MSG), i.e. the problem whether a given MSG specification is correctly distributable among parallel components communicating via messages. This fundamental problem of MSG is known to be undecidable. We introduce a well motivated restricted class of MSG, so called controllable-choice MSG, and show that all its models are realizable and moreover it is decidable whether a given MSG model is a member of this class. In more detail, this class of MSG specifications admits a deadlock-free realization by overloading existing messages with additional bounded control data. We also show that the presented class is the largest known subclass of MSG that allows for deadlock-free realization.
The paper considers the problem of model checking real-life VHDLbased hardware designs via their ... more The paper considers the problem of model checking real-life VHDLbased hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e., designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.
ABSTRACT To improve throughput of personal computers used as In-ternet routers, hardware accelera... more ABSTRACT To improve throughput of personal computers used as In-ternet routers, hardware acceleration can be used. Packet classification unit employed in the design utilizes content addressable memory com-bined with comparison instructions. Routing, link layer addressing, and packet filtering has to be performed in a single operation. We have de-veloped a representation of the first two called routing-ARP table, and representation of filters based on decision diagrams. In this paper, we describe a method to combine them all together and convert the resulting structure into the hardware device. As a special case, the algorithm converts a decision diagram into a first-match struc-ture. Dealing with implementation and limited hardware resources is mentioned.
We unify a view on three extensions of Process Rewrite Systems (PRS) and compare their expressive... more We unify a view on three extensions of Process Rewrite Systems (PRS) and compare their expressive power with that of PRS. We show that the class of Petri nets is less expressive up to bisimulation equivalence than the class of PA processes extended with a finite state control unit. Further we show our main result that the reachability problem for PRS extended with a so called weak finite state unit is decidable. wPRS r r r r r r r r r r r r r r r r r r r r r r r r K fcPRS r r r r r r r r r r r r r r r r r r r r r r r r K (G, G)-PRS r r r r r r r r r r r r r r r r r r r r r r r K r r r r r r r r r r r r r r r r r r r r r r r r
ABSTRACT We introduce improvements in the algorithm by Gastin and Oddoux translating LTL formulae... more ABSTRACT We introduce improvements in the algorithm by Gastin and Oddoux translating LTL formulae into B\"uchi automata via very weak alternating co-B\"uchi automata and generalized B\"uchi automata. Several improvements are based on specific properties of any formula where each branch of its syntax tree contains at least one eventually operator and at least one always operator. These changes usually result in faster translations and smaller automata. Other improvements reduce non-determinism in the produced automata. In fact, we modified all the steps of the original algorithm and its implementation known as LTL2BA. Experimental results show that our modifications are real improvements. Their implementations within an LTL2BA translation made LTL2BA very competitive with the current version of SPOT, sometimes outperforming it substantially.
This paper presents the verification of CRC algorithm properties. We examine a way of verifying o... more This paper presents the verification of CRC algorithm properties. We examine a way of verifying of a CRC algorithm using exhaustive state space exploration by model checking method. The CRC algorithm is used for calculation of a message hash value and we focus on verification of the property of finding minimal Hamming distance between two messages having the same hash value. We deal with 16, 32 and 64 bits CRC generator polynomials, especially with one used in the Liberouter project. ⋆ This research has been supported by the CESNET activity "Programmable hardware" .
We establish a decidability boundary of the model checking problem for infinitestate systems defi... more We establish a decidability boundary of the model checking problem for infinitestate systems defined by Process Rewrite Systems (PRS) or weakly extended Process Rewrite Systems (wPRS), and properties described by basic fragments of action-based Linear Temporal Logic (LTL) with both future and past operators. It is known that the problem for general LTL properties is decidable for Petri nets and for pushdown processes, while it is undecidable for PA processes. We show that the problem is decidable for wPRS if we consider properties defined by LTL formulae with only modalities strict eventually, strict always, and their past counterparts. Moreover, we show that the problem remains undecidable for PA processes even with respect to the LTL fragment with the only modality until or the fragment with modalities next and infinitely often. 2 L. Bozzelli et al.
We focus on the realizability problem of Message Sequence Graphs (MSG), i.e. the problem whether ... more We focus on the realizability problem of Message Sequence Graphs (MSG), i.e. the problem whether a given MSG specification is correctly distributable among parallel components communicating via messages. This fundamental problem of MSG is known to be undecidable. We introduce a well motivated restricted class of MSG, so called controllable-choice MSG, and show that all its models are realizable and moreover it is decidable whether a given MSG model is a member of this class. In more detail, this class of MSG specifications admits a deadlock-free realization by overloading existing messages with additional bounded control data. We also show that the presented class is the largest known subclass of MSG that allows for deadlock-free realization.
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Papers by V. Řehák