Proceedings Tenth International Conference on VLSI Design
Speeding up logic simulation is important to reduce design time of complex systems. Hardware emul... more Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems(RS) build using FPGA's offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose.
Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports hi... more Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient two-step genetic algorithm that has been used to build a tool for mapping an application, described by a parameterized task graph, on to a NoC architecture with a two dimensional mesh of switches as a communication backbone. The computational resources in NoC consists of a set of heterogenous IP cores. Our algorithm finds a mapping of the vertices of the task graph to available cores so that the overall execution time of the task graph is minimized. We have developed a NoC architecture specific communication delay model to estimate the execution time. Our algorithm is able to handle large task graphs and provide near optimal mapping in a few minutes on a PC platform. Our tool also provides facilities for specifying NoC architecture, generation and viewing synthetic task graphs and viewing the progress of the genetic algorithm as it converges to a solution.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Multi-FPGA boards are being used for logic emulation, rapid protooping, custom computing and low ... more Multi-FPGA boards are being used for logic emulation, rapid protooping, custom computing and low volume sub-system implementation. A key feature which characterizes these boards is their routing architecture(RA). Inter-FPGA connections in an RA can be of two types, namely ...
9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
Testing of high density SoCs operating at high clock speeds is an important but difficult problem... more Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for atspeed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing.
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002
We propose a packet switched platform for single chip systems which scales well to an arbitrary n... more We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical-architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
17th International Conference on VLSI Design. Proceedings.
We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) archit... more We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested and used. The concept includes support for best effort traffic packet delivery as well as for guaranteed bandwidth traffic using virtual circuits. Furthermore an application to NoC adapter is defined as part of the Resource to Network Interface, used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented and simulated and the results justifies the suggested layered approach.
At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very... more At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very important. Closely packed buses interconnecting cores are generally laid out on many interconnect layers to minimize area and delay. Aggressor-victim model is often used to represent the effect of crosstalk due to influence of one wire on the other. In this paper we propose an efficient method and corresponding BIST hardware for at-speed testing of such faults. The proposed BIST hardware is programmable and can provide a trade-off between test speed and test quality.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Improvement of the communication between components of a system which is integrated on a single c... more Improvement of the communication between components of a system which is integrated on a single chip. Motivations: In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing is very suitable in such contexts. Source routing has one serious drawback of overhead for storing the path information in header of every packet. This disadvantage becomes worse as the size of the network grows. A A technique, technique, called called Junction Junction Based Based Routing Routing (JBR), (JBR), can can handle handle this this problem problem.. Network on Chip (NoC) • The numbers of cores that can be integrated are growing linearly with the increase in chip capacity. • A dominant paradigm for synthesis of multi-core SoCs. • A packet switched network. • A NoC-based system is usually considered scalable. An Illustration of Using Junctions • This work considers 2-D mesh topology NoC for application of JBR. • The idea of JBR is general and will be applicable to all topologies-regular or irregular.
16th International Conference on VLSI Design, 2003. Proceedings.
Exploitation of silicon capacity will require improvements in design productivity and more scalab... more Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.
One way to specialize a general purpose multi-core chip built using NoC principles is to provide ... more One way to specialize a general purpose multi-core chip built using NoC principles is to provide a mechanism to configure an application specific deadlock free routing algorithm in the underlying communication network. A table in every router, implemented using a writable memory, can provide a possibility of specializing the routing algorithm according to the application requirements. In such an implementation the cost (area) of the router will be proportional to the size of the routing table. In this paper, we propose a method to compress the routing table to reduce its size such that the resulting routing algorithm remains deadlock free as well as has high adaptivity. We demonstrate through simulation based evaluation that our application specific routing algorithm gives much higher performance, in terms of latency and throughput, as compared to general purpose algorithms for deadlock free routing. We also show that a table size of two entries for each output port gives performance within 3% of the uncompressed table.
Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)
A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures ... more A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures is reported. We developed a library of predesigned modules that facilitate the assembly of independently clocked modules to on-chip systems. The components of this library establish high-performance data exchange channels which are instrumental in constructing flexible architectures. The validity of our concept is proven by applying it to an ASIC design
Percutaneous renal biopsy (PRB) can result in serious complications. The study is aimed to compar... more Percutaneous renal biopsy (PRB) can result in serious complications. The study is aimed to compare the biopsy yield and complications rate of the real-time ultrasonagram (USG)-guided PRB and needle tracking with and without needle guide in two different study periods. We compared the yield and complications of 2138 kidney biopsies performed in two different periods, 1510 biopsies during the first period from April 2004-December 2010 and 628 biopsies during second period from January 2011-March 2013. All biopsies in both periods were performed by nephrologists. Radiologists provided the real-time image without needle guide during the first period while nephrologists performed both imaging and biopsy with needle guide during the second period. Of all the 2138 patients, 226 (10.5%) patients developed 118 minor and 108 major complications. Only 13 (2.1%) major complications occurred in the second period and 95 (6.7%) in the first period (P < 0.001). The relative risk of developing a ...
Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype
A low-cost hybrid simulator for VLSI circuits has been under development at IIT Delhi. The simula... more A low-cost hybrid simulator for VLSI circuits has been under development at IIT Delhi. The simulator uses a Recongurable System (RS) consisting of a limited number of FPGAs for hardware emulation and blends the ideas of hardware emulation with conventional software simulation. A crucial preparatory step is to partition a given circuit into as few parts as possible. The parts are then downloaded onto the RS one by one and emulated in stand alone mode or in conjunction with software simulator. The hybrid simulation environment poses some unique requirements on the partitioner. This paper presents an ecient partitioning algorithm for this purpose. A study of performance of the algorithm on 32 benchmark circuits for various I/O and size constraints of FPGAs has been carried out and good results have been obtained.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
An important aspect of hardware-software co-design is partitioning of tasks to be scheduled on th... more An important aspect of hardware-software co-design is partitioning of tasks to be scheduled on the hardware and software resources. Existing approaches separate partitioning and scheduling in two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approaches may lead to sub-optimal results. In this paper, we present an integrated hardware/software scheduling, partitioning and binding strategy. We use dynamic programming techniques to devise an optimal solution for partitioning of a given concurrent task graph, which models the co-design problem, for execution on one software (single CPU) and several hardware resources (multiple FPGA's), with the objective of minimizing the total execution time. Our implementation shows that we can solve problem instances where the task graph has 40 nodes and 600 edges in less than a second.
The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing... more The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. It can also be helpful when analyzing and designing a large NoC as interconnection of subnets at a higher level of abstraction. Hierarchical deadlock-free routing is required to enable deadlock-free interconnection of sub-networks with different internal routing algorithms. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a two-level routing scheme, which is not only efficient, but also enables coexistence of algorithmic and table-based implementation in one router. A hierarchical view of the network simplifies addressing of network nodes and address decoding in the router. Synthesis results show that a 2-level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces, while keeping the properties of hierarchical deadlock-freedom. We evaluate and discuss the communication performance in a 2-level hierarchical network for various subnet interface setups and traffic situations. A cycle accurate simulator has been developed and used for this purpose.
In this paper we make a case for the use of NoC paradigm to develop future FPGAs in which large c... more In this paper we make a case for the use of NoC paradigm to develop future FPGAs in which large computational blocks (cores) are connected to each other through a packet switched communication network. We propose a methodology to develop efficient and deadlock free routing algorithms for such NoC platforms which can be specialized for an application or a set of concurrent applications. Application specific topology of communicating cores as well as information about their communication concurrency over time is exploited to maximize communication adaptivity and performance. We demonstrate, both through analysis of adaptivity as well as simulation based evaluation of latency and throughput, that our algorithm gives significantly higher performance as compared to general purpose deadlock free algorithms like XY and Odd-Even.
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009
Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hie... more Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hierarchical networks. In this paper, we propose a methodology for design of deadlock free routing algorithms for hierarchical networks, by combining routing algorithms of component subnets. Specifically, our methodology ensures reachability and deadlock freedom for the complete network if routing algorithms for subnets are deadlock free. We evaluate and compare the performance of hierarchical routing algorithms designed using our methodology with routing algorithms for corresponding flat networks. We show that hierarchical routing, combining best routing algorithm for each subnet, has a potential for providing better performance than using any single routing algorithm. This is observed for both synthetic as well as traffic from real applications. We also demonstrate, by measuring jitter in throughput, that hierarchical routing algorithms leads to smoother flow of network traffic. A router architecture that supports scalable table-based routing is briefly outlined.
Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototy... more Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototyping, custom computing and low volume sub-system implementation. Efficient use of an MFB does not only require a good routing topology, but also a good set of CAD tools to ...
Patients with history of solid organ/bone marrow transplantation, chronic renal failure and hyper... more Patients with history of solid organ/bone marrow transplantation, chronic renal failure and hypertension are known to present with a sudden neurological deficit and a multifactorial clinicoradiological syndrome called posterior reversible encephalopathy syndrome (PRES). Occurrence of vasogenic edema is well demonstrated on magnetic resonance imaging (MRI) which tends to resolve with medical therapy. Here we report a case of post-renal transplant recipient with graft failure showing typical manifestation of PRES and its successful medical management.
Proceedings Tenth International Conference on VLSI Design
Speeding up logic simulation is important to reduce design time of complex systems. Hardware emul... more Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems(RS) build using FPGA's offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose.
Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports hi... more Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient two-step genetic algorithm that has been used to build a tool for mapping an application, described by a parameterized task graph, on to a NoC architecture with a two dimensional mesh of switches as a communication backbone. The computational resources in NoC consists of a set of heterogenous IP cores. Our algorithm finds a mapping of the vertices of the task graph to available cores so that the overall execution time of the task graph is minimized. We have developed a NoC architecture specific communication delay model to estimate the execution time. Our algorithm is able to handle large task graphs and provide near optimal mapping in a few minutes on a PC platform. Our tool also provides facilities for specifying NoC architecture, generation and viewing synthetic task graphs and viewing the progress of the genetic algorithm as it converges to a solution.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Multi-FPGA boards are being used for logic emulation, rapid protooping, custom computing and low ... more Multi-FPGA boards are being used for logic emulation, rapid protooping, custom computing and low volume sub-system implementation. A key feature which characterizes these boards is their routing architecture(RA). Inter-FPGA connections in an RA can be of two types, namely ...
9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
Testing of high density SoCs operating at high clock speeds is an important but difficult problem... more Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for atspeed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing.
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002
We propose a packet switched platform for single chip systems which scales well to an arbitrary n... more We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical-architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
17th International Conference on VLSI Design. Proceedings.
We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) archit... more We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested and used. The concept includes support for best effort traffic packet delivery as well as for guaranteed bandwidth traffic using virtual circuits. Furthermore an application to NoC adapter is defined as part of the Resource to Network Interface, used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented and simulated and the results justifies the suggested layered approach.
At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very... more At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very important. Closely packed buses interconnecting cores are generally laid out on many interconnect layers to minimize area and delay. Aggressor-victim model is often used to represent the effect of crosstalk due to influence of one wire on the other. In this paper we propose an efficient method and corresponding BIST hardware for at-speed testing of such faults. The proposed BIST hardware is programmable and can provide a trade-off between test speed and test quality.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Improvement of the communication between components of a system which is integrated on a single c... more Improvement of the communication between components of a system which is integrated on a single chip. Motivations: In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing is very suitable in such contexts. Source routing has one serious drawback of overhead for storing the path information in header of every packet. This disadvantage becomes worse as the size of the network grows. A A technique, technique, called called Junction Junction Based Based Routing Routing (JBR), (JBR), can can handle handle this this problem problem.. Network on Chip (NoC) • The numbers of cores that can be integrated are growing linearly with the increase in chip capacity. • A dominant paradigm for synthesis of multi-core SoCs. • A packet switched network. • A NoC-based system is usually considered scalable. An Illustration of Using Junctions • This work considers 2-D mesh topology NoC for application of JBR. • The idea of JBR is general and will be applicable to all topologies-regular or irregular.
16th International Conference on VLSI Design, 2003. Proceedings.
Exploitation of silicon capacity will require improvements in design productivity and more scalab... more Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.
One way to specialize a general purpose multi-core chip built using NoC principles is to provide ... more One way to specialize a general purpose multi-core chip built using NoC principles is to provide a mechanism to configure an application specific deadlock free routing algorithm in the underlying communication network. A table in every router, implemented using a writable memory, can provide a possibility of specializing the routing algorithm according to the application requirements. In such an implementation the cost (area) of the router will be proportional to the size of the routing table. In this paper, we propose a method to compress the routing table to reduce its size such that the resulting routing algorithm remains deadlock free as well as has high adaptivity. We demonstrate through simulation based evaluation that our application specific routing algorithm gives much higher performance, in terms of latency and throughput, as compared to general purpose algorithms for deadlock free routing. We also show that a table size of two entries for each output port gives performance within 3% of the uncompressed table.
Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)
A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures ... more A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures is reported. We developed a library of predesigned modules that facilitate the assembly of independently clocked modules to on-chip systems. The components of this library establish high-performance data exchange channels which are instrumental in constructing flexible architectures. The validity of our concept is proven by applying it to an ASIC design
Percutaneous renal biopsy (PRB) can result in serious complications. The study is aimed to compar... more Percutaneous renal biopsy (PRB) can result in serious complications. The study is aimed to compare the biopsy yield and complications rate of the real-time ultrasonagram (USG)-guided PRB and needle tracking with and without needle guide in two different study periods. We compared the yield and complications of 2138 kidney biopsies performed in two different periods, 1510 biopsies during the first period from April 2004-December 2010 and 628 biopsies during second period from January 2011-March 2013. All biopsies in both periods were performed by nephrologists. Radiologists provided the real-time image without needle guide during the first period while nephrologists performed both imaging and biopsy with needle guide during the second period. Of all the 2138 patients, 226 (10.5%) patients developed 118 minor and 108 major complications. Only 13 (2.1%) major complications occurred in the second period and 95 (6.7%) in the first period (P < 0.001). The relative risk of developing a ...
Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype
A low-cost hybrid simulator for VLSI circuits has been under development at IIT Delhi. The simula... more A low-cost hybrid simulator for VLSI circuits has been under development at IIT Delhi. The simulator uses a Recongurable System (RS) consisting of a limited number of FPGAs for hardware emulation and blends the ideas of hardware emulation with conventional software simulation. A crucial preparatory step is to partition a given circuit into as few parts as possible. The parts are then downloaded onto the RS one by one and emulated in stand alone mode or in conjunction with software simulator. The hybrid simulation environment poses some unique requirements on the partitioner. This paper presents an ecient partitioning algorithm for this purpose. A study of performance of the algorithm on 32 benchmark circuits for various I/O and size constraints of FPGAs has been carried out and good results have been obtained.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
An important aspect of hardware-software co-design is partitioning of tasks to be scheduled on th... more An important aspect of hardware-software co-design is partitioning of tasks to be scheduled on the hardware and software resources. Existing approaches separate partitioning and scheduling in two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approaches may lead to sub-optimal results. In this paper, we present an integrated hardware/software scheduling, partitioning and binding strategy. We use dynamic programming techniques to devise an optimal solution for partitioning of a given concurrent task graph, which models the co-design problem, for execution on one software (single CPU) and several hardware resources (multiple FPGA's), with the objective of minimizing the total execution time. Our implementation shows that we can solve problem instances where the task graph has 40 nodes and 600 edges in less than a second.
The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing... more The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. It can also be helpful when analyzing and designing a large NoC as interconnection of subnets at a higher level of abstraction. Hierarchical deadlock-free routing is required to enable deadlock-free interconnection of sub-networks with different internal routing algorithms. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a two-level routing scheme, which is not only efficient, but also enables coexistence of algorithmic and table-based implementation in one router. A hierarchical view of the network simplifies addressing of network nodes and address decoding in the router. Synthesis results show that a 2-level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces, while keeping the properties of hierarchical deadlock-freedom. We evaluate and discuss the communication performance in a 2-level hierarchical network for various subnet interface setups and traffic situations. A cycle accurate simulator has been developed and used for this purpose.
In this paper we make a case for the use of NoC paradigm to develop future FPGAs in which large c... more In this paper we make a case for the use of NoC paradigm to develop future FPGAs in which large computational blocks (cores) are connected to each other through a packet switched communication network. We propose a methodology to develop efficient and deadlock free routing algorithms for such NoC platforms which can be specialized for an application or a set of concurrent applications. Application specific topology of communicating cores as well as information about their communication concurrency over time is exploited to maximize communication adaptivity and performance. We demonstrate, both through analysis of adaptivity as well as simulation based evaluation of latency and throughput, that our algorithm gives significantly higher performance as compared to general purpose deadlock free algorithms like XY and Odd-Even.
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009
Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hie... more Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hierarchical networks. In this paper, we propose a methodology for design of deadlock free routing algorithms for hierarchical networks, by combining routing algorithms of component subnets. Specifically, our methodology ensures reachability and deadlock freedom for the complete network if routing algorithms for subnets are deadlock free. We evaluate and compare the performance of hierarchical routing algorithms designed using our methodology with routing algorithms for corresponding flat networks. We show that hierarchical routing, combining best routing algorithm for each subnet, has a potential for providing better performance than using any single routing algorithm. This is observed for both synthetic as well as traffic from real applications. We also demonstrate, by measuring jitter in throughput, that hierarchical routing algorithms leads to smoother flow of network traffic. A router architecture that supports scalable table-based routing is briefly outlined.
Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototy... more Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototyping, custom computing and low volume sub-system implementation. Efficient use of an MFB does not only require a good routing topology, but also a good set of CAD tools to ...
Patients with history of solid organ/bone marrow transplantation, chronic renal failure and hyper... more Patients with history of solid organ/bone marrow transplantation, chronic renal failure and hypertension are known to present with a sudden neurological deficit and a multifactorial clinicoradiological syndrome called posterior reversible encephalopathy syndrome (PRES). Occurrence of vasogenic edema is well demonstrated on magnetic resonance imaging (MRI) which tends to resolve with medical therapy. Here we report a case of post-renal transplant recipient with graft failure showing typical manifestation of PRES and its successful medical management.
Uploads
Papers by Shashi Kumar