Proceedings the European Design and Test Conference. ED&TC 1995, 1995
... Dennis J.-H. Huang and Andrew B. Kahng, “When Clusters Meet Partitions: New Density-Based Met... more ... Dennis J.-H. Huang and Andrew B. Kahng, “When Clusters Meet Partitions: New Density-Based Meth-ods for Circuit Decomposition”, UCLA Computer Sci-ence ... J.-C. Picard, “Maximal Closure of a Graph and AppIi-cation to Combinatorial Problems”, Management Sci-ence, Vol ...
Bidirectional search and heuristic search are techniques that improve the performance of a shorte... more Bidirectional search and heuristic search are techniques that improve the performance of a shortest path graph search. Despite many attempts to use both at the same time, this combination had been leading to worse results in average, compared to the classic unidirectional heuristic A* algorithm. In[4], a new graph search algorithm was developed LCS*, that is the first to combine these techniques effectively. LCS* is a generic and simultaneous bidirectional heuristic algorithm which is faster than A* in most domains. This work present formal proofs of the completeness and admissibility of LCS*.
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layou... more To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add ll geometries, either at the foundry or, for better convergence of performance veri cation ows, during layout synthesis 10]. This paper proposes a new min-variation objective for the synthesis of ll geometries. Within the so-called xed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for ll pattern synthesis, and discuss additional criteria that apply when ll must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994
We pr ovide a new theoretical framework for constructing Steiner routing trees with minimum Elmor... more We pr ovide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work has established Elmore delay as a high delity estimate of \physical", i.e., SPICEcomputed, signal delay. Previously, however, it was not known how to construct an Elmore delay-optimal Steiner tree. Our main theoretical result is a generalization of Hanan's theorem [11] which limited the number of possible locations of Steiner nodes in an optimal delay rectilinear Steiner tree. Another theoretical result establishes a new decomposition theorem for constructing optimal-delay Steiner trees. We develop a br anch-andbound method, called BB-SORT-C, which exactly minimizes any linear combination of Elmore sink delays; BB-SORT-C is practical for routing small nets and for delimiting the space of achievable routing solutions with respect to Elmore delay.
Journal of computational biology : a journal of computational molecular cell biology, 2004
Design of DNA arrays for very large-scale immobilized polymer synthesis (VLSIPS) (Fodor et al., 1... more Design of DNA arrays for very large-scale immobilized polymer synthesis (VLSIPS) (Fodor et al., 1991) seeks to minimize effects of unintended illumination during mask exposure steps. Hannenhalli et al. (2002) formulate this requirement as the Border Minimization Problem and give an algorithm for placement of probes at array sites under the assumption that the array synthesis is synchronous; i.e., nucleotides are synthesized in a periodic sequence (ACGT)(k) and every probe grows by exactly one nucleotide with every group of four masks. Drawing on the analogy with VLSI placement, in this paper we describe and experimentally validate the engineering of several scalable, high-quality placement heuristics for both synchronous and asynchronous DNA array design. We give empirical results on both randomly generated and industry test cases confirming the scalability and improved solution quality enjoyed by our methods. In general, our techniques improve on state-of-the-art industrial results...
Proceedings of the 1998 international symposium on Physical design - ISPD '98, 1998
In very deep-submicron VLSI, certain manufacturing steps -notably optical exposure, resist develo... more In very deep-submicron VLSI, certain manufacturing steps -notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)-have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion ("filling") or partial deletion ("slotting") of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future placeand-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
High Performance Clock Distribution Networks, 1997
In Clock routing research, such practical considerations as hierarchical buffering, rise-time and... more In Clock routing research, such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacle-and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying layer parasitics with non-zero via parasitics; (ii) obstacle-avoidance clock routing; and (iii) hierarchical buffered tree synthesis. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches.
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
We present critical-sink routing tree (CSRT) constructions which yield high-performance routing t... more We present critical-sink routing tree (CSRT) constructions which yield high-performance routing trees by exploiting the critical-path information that may be available during timing-driven layout. Motivated by analysis of the Elmore delay formula, we propose the CS-Steiner class of heuristics and a \Global Slack Removal" algorithm; these modify traditional Steiner tree constructions to optimize signal delay at identi ed critical sinks. Extensive timing simulations, using industry IC and MCM technology parameters and a fast simulator based on a 2-pole distributed RCL delay approximation 29], show that this simple approach a ords very signi cant improvements over existing \performance-driven" routing tree constructions. Next, we observe that all existing routing tree objectives (e.g., minimum-cost Steiner 16] or bounded-radius 5]) are heuristic abstractions of the linear or Elmore delay models. We therefore propose a new class of e cient Elmore routing tree (ERT) constructions, which iteratively add tree edges that are optimal in terms of Elmore delay. For the CSRT problem, this direct optimization of Elmore delay yields trees that signi cantly improve (by averages of up to 69%) upon minimum Steiner routings in terms of delays to identi ed critical sinks. Moreover, ERTs serve as generic high-performance routing trees when no critical sink is speci ed: for 8-sink nets in 0:8 CMOS IC technology, we improve average sink delay by 10% and maximum delay by 13% over the minimum Steiner routing. For a typical MCM technology, the corresponding improvements are 42% and 22%. The ERT approach represents a basic advance over existing performance-driven routing tree constructions, including such recent works as 1] 4] 5].
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
We study the minimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. Th... more We study the minimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region.
How can design teams employ new tools and develop response methodologies yet still stay within de... more How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
ABSTRACT Approximation can increase performance or reduce power consumption with a simplified or ... more ABSTRACT Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.
International Conference on Computer Aided Design, 2003
DNA probe arrays have emerged as a core genomic technology thatenables cost-effective gene expres... more DNA probe arrays have emerged as a core genomic technology thatenables cost-effective gene expression monitoring, mutation detection,single nucleotide polymorphism analysis and other genomicanalyses. DNA chips are manufactured through a highly scalableprocess, Very Large-Scale Immobilized Polymer Synthesis (VL-SIPS),that combines photolithographic technologies adapted fromthe semiconductor industry with combinatorial chemistry. Commerciallyavailable DNA chips contain more than a half millionprobes and are expected to
International Conference on Computer Aided Design, 2008
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two... more In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In
Robust power distribution within available routing area resources is critical to chip performance... more Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for optimizing worst-case static IR-drop in hierarchical, uniform power distribution networks. Our results can be used for planning of hierarchical power distribution in early design stages, so that for a fixed total routing area the worst-case IR-drop on the power mesh is minimal, or for a given IR-drop tolerance the power mesh achieves the IR-drop specification with minimal routing area. Our contributions are as follows. (1) We derive a closed-form approximation for the worst-case IR-drop on a single-level power mesh. The formula shows that for a given total routing area, the worst-case
In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, tw... more In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45 nm testcases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill sy... more We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very large-scale integration metallization processes. Post-CMP wafer topography varies according to pattern density. We review density-analysis methods and density-control objectives that are used in
We address robust path planning for a mobile agent in a general environment by nding minimum cost... more We address robust path planning for a mobile agent in a general environment by nding minimum cost source-destination paths having prescribed widths. The main result is a new approach which optimally solves the robust path planning problem using an e cient network ow formulation. Our algorithm represents a signi cant departure from conventional shortest-path or graph search based methods; it not only handles environments with solid polygonal obstacles but also generalizes to arbitrary cost maps which may arise in modeling incomplete or uncertain knowledge of the environment. Simple extensions allow us to address higher-dimensional problem instances and minimum-surface computations; the latter is a result of independent interest. We use an e cient implementation to exhibit optimal path-planning solutions for a variety of test problems. The paper concludes with open issues and directions for future work.
Spectral geometric embeddings of a circuit netlist can lead to fast, high quality m ulti-way part... more Spectral geometric embeddings of a circuit netlist can lead to fast, high quality m ulti-way partitioning solutions. Furthermore, it has been shown that d-dimensional spectral embeddings (d > 1) are a more powerful tool than single-eigenvector embeddings (d = 1) for multi-way partitioning [2] [4]. However, previous methods cannot fully utilize information from the spectral embedding while optimizing netlist-dependent objectives. This work introduces a new multi-way circuit partitioning algorithm called DP-RP. W e begin with a d-dimensional spectral embedding from which a 1-dimensional ordering of the modules is obtained using a spacelling curve. The 1dimensional ordering retains useful information from the multi-dimensional embedding while allowing application of ecient algorithms. We show that for a new Restricted Partitioning formulation, dynamic programming eciently nds optimal solutions in terms of Scaled Cost [4] and can transparently handle userspecied cluster size constraints. For 2-way ratio cut partitioning, DP-RP yields an average of 45% improvement o v er KP [4] and EIG1 [6] and 48% improvement o v er KC [ 2 ].
We present a general framework for the construction of vertex orderings for netlist clustering. O... more We present a general framework for the construction of vertex orderings for netlist clustering. Our WINDOW algorithm constructs an ordering by iteratively adding the vertex with highest attraction to the existing ordering. Variant c hoices for the attraction function allow our framework to subsume many graph traversals and clustering objectives from the literature. The DP-RP method of [3] is then applied to optimally split the ordering into a k-way clustering. Our approach is adaptable to user-specied cluster size constraints. Experimental results for clustering and multi-way partitioning are encouraging.
Proceedings the European Design and Test Conference. ED&TC 1995, 1995
... Dennis J.-H. Huang and Andrew B. Kahng, “When Clusters Meet Partitions: New Density-Based Met... more ... Dennis J.-H. Huang and Andrew B. Kahng, “When Clusters Meet Partitions: New Density-Based Meth-ods for Circuit Decomposition”, UCLA Computer Sci-ence ... J.-C. Picard, “Maximal Closure of a Graph and AppIi-cation to Combinatorial Problems”, Management Sci-ence, Vol ...
Bidirectional search and heuristic search are techniques that improve the performance of a shorte... more Bidirectional search and heuristic search are techniques that improve the performance of a shortest path graph search. Despite many attempts to use both at the same time, this combination had been leading to worse results in average, compared to the classic unidirectional heuristic A* algorithm. In[4], a new graph search algorithm was developed LCS*, that is the first to combine these techniques effectively. LCS* is a generic and simultaneous bidirectional heuristic algorithm which is faster than A* in most domains. This work present formal proofs of the completeness and admissibility of LCS*.
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layou... more To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add ll geometries, either at the foundry or, for better convergence of performance veri cation ows, during layout synthesis 10]. This paper proposes a new min-variation objective for the synthesis of ll geometries. Within the so-called xed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for ll pattern synthesis, and discuss additional criteria that apply when ll must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994
We pr ovide a new theoretical framework for constructing Steiner routing trees with minimum Elmor... more We pr ovide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work has established Elmore delay as a high delity estimate of \physical", i.e., SPICEcomputed, signal delay. Previously, however, it was not known how to construct an Elmore delay-optimal Steiner tree. Our main theoretical result is a generalization of Hanan's theorem [11] which limited the number of possible locations of Steiner nodes in an optimal delay rectilinear Steiner tree. Another theoretical result establishes a new decomposition theorem for constructing optimal-delay Steiner trees. We develop a br anch-andbound method, called BB-SORT-C, which exactly minimizes any linear combination of Elmore sink delays; BB-SORT-C is practical for routing small nets and for delimiting the space of achievable routing solutions with respect to Elmore delay.
Journal of computational biology : a journal of computational molecular cell biology, 2004
Design of DNA arrays for very large-scale immobilized polymer synthesis (VLSIPS) (Fodor et al., 1... more Design of DNA arrays for very large-scale immobilized polymer synthesis (VLSIPS) (Fodor et al., 1991) seeks to minimize effects of unintended illumination during mask exposure steps. Hannenhalli et al. (2002) formulate this requirement as the Border Minimization Problem and give an algorithm for placement of probes at array sites under the assumption that the array synthesis is synchronous; i.e., nucleotides are synthesized in a periodic sequence (ACGT)(k) and every probe grows by exactly one nucleotide with every group of four masks. Drawing on the analogy with VLSI placement, in this paper we describe and experimentally validate the engineering of several scalable, high-quality placement heuristics for both synchronous and asynchronous DNA array design. We give empirical results on both randomly generated and industry test cases confirming the scalability and improved solution quality enjoyed by our methods. In general, our techniques improve on state-of-the-art industrial results...
Proceedings of the 1998 international symposium on Physical design - ISPD '98, 1998
In very deep-submicron VLSI, certain manufacturing steps -notably optical exposure, resist develo... more In very deep-submicron VLSI, certain manufacturing steps -notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)-have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion ("filling") or partial deletion ("slotting") of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future placeand-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
High Performance Clock Distribution Networks, 1997
In Clock routing research, such practical considerations as hierarchical buffering, rise-time and... more In Clock routing research, such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacle-and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying layer parasitics with non-zero via parasitics; (ii) obstacle-avoidance clock routing; and (iii) hierarchical buffered tree synthesis. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches.
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
We present critical-sink routing tree (CSRT) constructions which yield high-performance routing t... more We present critical-sink routing tree (CSRT) constructions which yield high-performance routing trees by exploiting the critical-path information that may be available during timing-driven layout. Motivated by analysis of the Elmore delay formula, we propose the CS-Steiner class of heuristics and a \Global Slack Removal" algorithm; these modify traditional Steiner tree constructions to optimize signal delay at identi ed critical sinks. Extensive timing simulations, using industry IC and MCM technology parameters and a fast simulator based on a 2-pole distributed RCL delay approximation 29], show that this simple approach a ords very signi cant improvements over existing \performance-driven" routing tree constructions. Next, we observe that all existing routing tree objectives (e.g., minimum-cost Steiner 16] or bounded-radius 5]) are heuristic abstractions of the linear or Elmore delay models. We therefore propose a new class of e cient Elmore routing tree (ERT) constructions, which iteratively add tree edges that are optimal in terms of Elmore delay. For the CSRT problem, this direct optimization of Elmore delay yields trees that signi cantly improve (by averages of up to 69%) upon minimum Steiner routings in terms of delays to identi ed critical sinks. Moreover, ERTs serve as generic high-performance routing trees when no critical sink is speci ed: for 8-sink nets in 0:8 CMOS IC technology, we improve average sink delay by 10% and maximum delay by 13% over the minimum Steiner routing. For a typical MCM technology, the corresponding improvements are 42% and 22%. The ERT approach represents a basic advance over existing performance-driven routing tree constructions, including such recent works as 1] 4] 5].
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
We study the minimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. Th... more We study the minimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region.
How can design teams employ new tools and develop response methodologies yet still stay within de... more How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
ABSTRACT Approximation can increase performance or reduce power consumption with a simplified or ... more ABSTRACT Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.
International Conference on Computer Aided Design, 2003
DNA probe arrays have emerged as a core genomic technology thatenables cost-effective gene expres... more DNA probe arrays have emerged as a core genomic technology thatenables cost-effective gene expression monitoring, mutation detection,single nucleotide polymorphism analysis and other genomicanalyses. DNA chips are manufactured through a highly scalableprocess, Very Large-Scale Immobilized Polymer Synthesis (VL-SIPS),that combines photolithographic technologies adapted fromthe semiconductor industry with combinatorial chemistry. Commerciallyavailable DNA chips contain more than a half millionprobes and are expected to
International Conference on Computer Aided Design, 2008
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two... more In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In
Robust power distribution within available routing area resources is critical to chip performance... more Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for optimizing worst-case static IR-drop in hierarchical, uniform power distribution networks. Our results can be used for planning of hierarchical power distribution in early design stages, so that for a fixed total routing area the worst-case IR-drop on the power mesh is minimal, or for a given IR-drop tolerance the power mesh achieves the IR-drop specification with minimal routing area. Our contributions are as follows. (1) We derive a closed-form approximation for the worst-case IR-drop on a single-level power mesh. The formula shows that for a given total routing area, the worst-case
In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, tw... more In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45 nm testcases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill sy... more We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very large-scale integration metallization processes. Post-CMP wafer topography varies according to pattern density. We review density-analysis methods and density-control objectives that are used in
We address robust path planning for a mobile agent in a general environment by nding minimum cost... more We address robust path planning for a mobile agent in a general environment by nding minimum cost source-destination paths having prescribed widths. The main result is a new approach which optimally solves the robust path planning problem using an e cient network ow formulation. Our algorithm represents a signi cant departure from conventional shortest-path or graph search based methods; it not only handles environments with solid polygonal obstacles but also generalizes to arbitrary cost maps which may arise in modeling incomplete or uncertain knowledge of the environment. Simple extensions allow us to address higher-dimensional problem instances and minimum-surface computations; the latter is a result of independent interest. We use an e cient implementation to exhibit optimal path-planning solutions for a variety of test problems. The paper concludes with open issues and directions for future work.
Spectral geometric embeddings of a circuit netlist can lead to fast, high quality m ulti-way part... more Spectral geometric embeddings of a circuit netlist can lead to fast, high quality m ulti-way partitioning solutions. Furthermore, it has been shown that d-dimensional spectral embeddings (d > 1) are a more powerful tool than single-eigenvector embeddings (d = 1) for multi-way partitioning [2] [4]. However, previous methods cannot fully utilize information from the spectral embedding while optimizing netlist-dependent objectives. This work introduces a new multi-way circuit partitioning algorithm called DP-RP. W e begin with a d-dimensional spectral embedding from which a 1-dimensional ordering of the modules is obtained using a spacelling curve. The 1dimensional ordering retains useful information from the multi-dimensional embedding while allowing application of ecient algorithms. We show that for a new Restricted Partitioning formulation, dynamic programming eciently nds optimal solutions in terms of Scaled Cost [4] and can transparently handle userspecied cluster size constraints. For 2-way ratio cut partitioning, DP-RP yields an average of 45% improvement o v er KP [4] and EIG1 [6] and 48% improvement o v er KC [ 2 ].
We present a general framework for the construction of vertex orderings for netlist clustering. O... more We present a general framework for the construction of vertex orderings for netlist clustering. Our WINDOW algorithm constructs an ordering by iteratively adding the vertex with highest attraction to the existing ordering. Variant c hoices for the attraction function allow our framework to subsume many graph traversals and clustering objectives from the literature. The DP-RP method of [3] is then applied to optimally split the ordering into a k-way clustering. Our approach is adaptable to user-specied cluster size constraints. Experimental results for clustering and multi-way partitioning are encouraging.
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Papers by Andrew Kahng