The Fourier law for lattice heat conduction fails when the source of heat is small compared to th... more The Fourier law for lattice heat conduction fails when the source of heat is small compared to the phonon mean free path. We provide experimental evidence for this effect using heating and electrical-resistance thermometry along a doped region in a suspended silicon membrane. The data are consistent with a closed-form two-fluid phonon conduction model, which accounts for the severe departure from equilibrium at the hotspot. The temperature rise exceeds predictions based on the Fourier law by 60% when the phonon mean free path is a factor of 30 larger than the resistor thickness. This work is improving the constitutive modeling of heat flow in deep-submicron transistors.
Intense electron-phonon scattering near the peak electric field in a semiconductor device results... more Intense electron-phonon scattering near the peak electric field in a semiconductor device results in nanometer-scale phonon hotspots. Past studies have argued that ballistic phonon transport near such hotspots serves to restrict heat conduction. We reexamine this assertion by developing a new phonon transport model. In a departure from previous studies, we treat isotropic dispersion in all phonon branches and include a phonon emission spectrum from independent Monte Carlo simulations of electron-phonon scattering. We cast the model in terms of a non-equilibrium phonon distribution function and compare predictions from this model with data for ballistic transport in silicon. The solution to the steady-state transport equations for bulk silicon transistors shows that energy stagnation at the hotspot results in an excess equivalent temperature rise of about 13% in a 90 nm gate-length device. Longitudinal optical phonons with non-zero group velocities dominate transport. We find that the resistance associated with ballistic transport does not overwhelm that from the package unless the peak power density approaches 50 W / m 3 . A transient calculation shows negligible phonon accumulation and retardation between successive logic states. This work highlights and reduces the knowledge gaps in the electro-thermal simulation of transistors.
| As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becomin... more | As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004
This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We in... more This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a selfconsistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that the intrinsic gate delay (CV /I) is optimal. We find that a raised source/drain height approximately 3 times the channel thickness would be desirable both from an electrical and thermal point of view. Optimized GOI devices could provide at least 30 percent performance advantage over similar SOI devices, despite the lower thermal conductivity of the germanium layer.
Existing theory and data cannot quantify the contribution of phonon drag to the Seebeck coefficie... more Existing theory and data cannot quantify the contribution of phonon drag to the Seebeck coefficient (S) in semiconductors at room temperature. We show that this is possible through comparative measurements between nanowires and the bulk. Phonon boundary scattering completely quenches phonon drag in silicon nanowires enabling quantification of its contribution to S in bulk silicon in the range 25-500 K. The contribution is surprisingly large (~34%) at 300 K even at doping of ~3x10^19 cm-3. Our results contradict the notion that phonon drag is negligible in degenerate semiconductors at temperatures relevant for thermoelectric energy conversion. A revised theory of electron-phonon momentum exchange that accounts for a phonon mean free path spectrum agrees well with the data.
This work develops a Monte Carlo (MC) simulation method for calculating the heat generation rate ... more This work develops a Monte Carlo (MC) simulation method for calculating the heat generation rate in electronic nanostructures. Electrons accelerated by the electric field scatter strongly with optical phonons, yet heat transport in silicon occurs via the faster acoustic modes. The MC method incorporates the appropriate energy transfer rates from electrons to each phonon branch. This accounts for the non-equilibrium energy exchange between the electrons and phonon branches. Using the MC method with an electron energy-dependent scattering rate intrinsically accounts for the non-locality of the heat transfer near a strongly peaked electric field. This approach provides more information about electronically generated heat at nanoscale dimensions compared to traditional macroscopic field-dependent methods. The method has applications in any region of high spatial or temporal non-equilibrium between electrons and phonons, and particularly facilitates careful microscopic analysis of heating in a nanoscale transistor.
The electronics industry is encountering thermal challenges and opportunities with lengthscales c... more The electronics industry is encountering thermal challenges and opportunities with lengthscales comparable to or much less than one micrometer. Examples include nanoscale phonon hotspots in transistors and the increasing temperature rise in on- chip interconnects. Millimeter-scale hotspots on microprocessors, resulting from varying rates of power consumption, are being addressed using two-phase microchannel heat sinks. Nanoscale thermal data storage technology has
Top-down electroless chemical etching enables non-lithographic patterning of wafer-scale nanostru... more Top-down electroless chemical etching enables non-lithographic patterning of wafer-scale nanostructured arrays, but the etching on highly doped wafers produces porous structures. The lack of defect-free nanostructures at desired doping and the difficulties in forming reliable electrical side-contacts to the nanostructure arrays limits their integration into high performance nanoelectronics. We developed a barrier layer diffusion technique to controllably dope wafer-scale silicon nanowire arrays (10(17)-10(20) cm(-3)) produced by chemically etching lightly doped silicon wafers. In order to achieve low resistance top-side electrical contacts to the arrays, we developed a two step tip-doping procedure to locally dope the tips (∼10(20) cm(-3)) to metallic levels. The dopant concentration is characterized by depth profiling using secondary ion mass spectroscopy and four-point probe electrical measurements. Further, array scale electrical measurements show that the tip-doping lowers the specific contact resistivity (∼10(-5) Ω cm(2)) since the metallic tips enable direct tunneling of electrons across the nickel silicide contacts to the nanowire arrays. This work provides a scalable and cost-effective doping approach to control charge injection and charge conduction in nanowire arrays, thus advancing their integration into various device applications.
Frontiers in Electronics - Proceedings of the WOFE-04, 2006
Recent trends in processor power for the next generation devices point clearly to significant inc... more Recent trends in processor power for the next generation devices point clearly to significant increase in processor heat dissipation over the coming years. In the desktop system design space, the tendency has been to minimize system enclosure size while maximizing performance, which in turn leads to high power densities in future generation systems. The current thermal solutions used today consist of advanced heat sink designs and heat pipe designs with forced air cooling to cool high power processors. However, these techniques are already reaching their limits to handle high heat flux, and there is a strong need for development of more efficient cooling systems which are scalable to handle the high heat flux generated by the future products. To meet this challenge, there has been research in academia and in industry to explore alternative methods for extracting heat from high-density power sources in electronic systems. This talk will discuss the issues surrounding device cooling, from the transistor level to the system level, and describe system-level solutions being developed for desktop computer applications developed in our group at Stanford University.
International Journal of High Speed Electronics and Systems, 2006
Recent trends in processor power for the next generation devices point clearly to significant inc... more Recent trends in processor power for the next generation devices point clearly to significant increase in processor heat dissipation over the coming years. In the desktop system design space, the tendency has been to minimize system enclosure size while maximizing performance, which in turn leads to high power densities in future generation systems. The current thermal solutions used today consist of advanced heat sink designs and heat pipe designs with forced air cooling to cool high power processors. However, these techniques are already reaching their limits to handle high heat flux, and there is a strong need for development of more efficient cooling systems which are scalable to handle the high heat flux generated by the future products. To meet this challenge, there has been research in academia and in industry to explore alternative methods for extracting heat from high-density power sources in electronic systems. This talk will discuss the issues surrounding device cooling, from the transistor level to the system level, and describe system-level solutions being developed for desktop computer applications developed in our group at Stanford University.
The Fourier law for lattice heat conduction fails when the source of heat is small compared to th... more The Fourier law for lattice heat conduction fails when the source of heat is small compared to the phonon mean free path. We provide experimental evidence for this effect using heating and electrical-resistance thermometry along a doped region in a suspended silicon membrane. The data are consistent with a closed-form two-fluid phonon conduction model, which accounts for the severe departure from equilibrium at the hotspot. The temperature rise exceeds predictions based on the Fourier law by 60% when the phonon mean free path is a factor of 30 larger than the resistor thickness. This work is improving the constitutive modeling of heat flow in deep-submicron transistors.
Intense electron-phonon scattering near the peak electric field in a semiconductor device results... more Intense electron-phonon scattering near the peak electric field in a semiconductor device results in nanometer-scale phonon hotspots. Past studies have argued that ballistic phonon transport near such hotspots serves to restrict heat conduction. We reexamine this assertion by developing a new phonon transport model. In a departure from previous studies, we treat isotropic dispersion in all phonon branches and include a phonon emission spectrum from independent Monte Carlo simulations of electron-phonon scattering. We cast the model in terms of a non-equilibrium phonon distribution function and compare predictions from this model with data for ballistic transport in silicon. The solution to the steady-state transport equations for bulk silicon transistors shows that energy stagnation at the hotspot results in an excess equivalent temperature rise of about 13% in a 90 nm gate-length device. Longitudinal optical phonons with non-zero group velocities dominate transport. We find that the resistance associated with ballistic transport does not overwhelm that from the package unless the peak power density approaches 50 W / m 3 . A transient calculation shows negligible phonon accumulation and retardation between successive logic states. This work highlights and reduces the knowledge gaps in the electro-thermal simulation of transistors.
| As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becomin... more | As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004
This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We in... more This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a selfconsistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that the intrinsic gate delay (CV /I) is optimal. We find that a raised source/drain height approximately 3 times the channel thickness would be desirable both from an electrical and thermal point of view. Optimized GOI devices could provide at least 30 percent performance advantage over similar SOI devices, despite the lower thermal conductivity of the germanium layer.
Existing theory and data cannot quantify the contribution of phonon drag to the Seebeck coefficie... more Existing theory and data cannot quantify the contribution of phonon drag to the Seebeck coefficient (S) in semiconductors at room temperature. We show that this is possible through comparative measurements between nanowires and the bulk. Phonon boundary scattering completely quenches phonon drag in silicon nanowires enabling quantification of its contribution to S in bulk silicon in the range 25-500 K. The contribution is surprisingly large (~34%) at 300 K even at doping of ~3x10^19 cm-3. Our results contradict the notion that phonon drag is negligible in degenerate semiconductors at temperatures relevant for thermoelectric energy conversion. A revised theory of electron-phonon momentum exchange that accounts for a phonon mean free path spectrum agrees well with the data.
This work develops a Monte Carlo (MC) simulation method for calculating the heat generation rate ... more This work develops a Monte Carlo (MC) simulation method for calculating the heat generation rate in electronic nanostructures. Electrons accelerated by the electric field scatter strongly with optical phonons, yet heat transport in silicon occurs via the faster acoustic modes. The MC method incorporates the appropriate energy transfer rates from electrons to each phonon branch. This accounts for the non-equilibrium energy exchange between the electrons and phonon branches. Using the MC method with an electron energy-dependent scattering rate intrinsically accounts for the non-locality of the heat transfer near a strongly peaked electric field. This approach provides more information about electronically generated heat at nanoscale dimensions compared to traditional macroscopic field-dependent methods. The method has applications in any region of high spatial or temporal non-equilibrium between electrons and phonons, and particularly facilitates careful microscopic analysis of heating in a nanoscale transistor.
The electronics industry is encountering thermal challenges and opportunities with lengthscales c... more The electronics industry is encountering thermal challenges and opportunities with lengthscales comparable to or much less than one micrometer. Examples include nanoscale phonon hotspots in transistors and the increasing temperature rise in on- chip interconnects. Millimeter-scale hotspots on microprocessors, resulting from varying rates of power consumption, are being addressed using two-phase microchannel heat sinks. Nanoscale thermal data storage technology has
Top-down electroless chemical etching enables non-lithographic patterning of wafer-scale nanostru... more Top-down electroless chemical etching enables non-lithographic patterning of wafer-scale nanostructured arrays, but the etching on highly doped wafers produces porous structures. The lack of defect-free nanostructures at desired doping and the difficulties in forming reliable electrical side-contacts to the nanostructure arrays limits their integration into high performance nanoelectronics. We developed a barrier layer diffusion technique to controllably dope wafer-scale silicon nanowire arrays (10(17)-10(20) cm(-3)) produced by chemically etching lightly doped silicon wafers. In order to achieve low resistance top-side electrical contacts to the arrays, we developed a two step tip-doping procedure to locally dope the tips (∼10(20) cm(-3)) to metallic levels. The dopant concentration is characterized by depth profiling using secondary ion mass spectroscopy and four-point probe electrical measurements. Further, array scale electrical measurements show that the tip-doping lowers the specific contact resistivity (∼10(-5) Ω cm(2)) since the metallic tips enable direct tunneling of electrons across the nickel silicide contacts to the nanowire arrays. This work provides a scalable and cost-effective doping approach to control charge injection and charge conduction in nanowire arrays, thus advancing their integration into various device applications.
Frontiers in Electronics - Proceedings of the WOFE-04, 2006
Recent trends in processor power for the next generation devices point clearly to significant inc... more Recent trends in processor power for the next generation devices point clearly to significant increase in processor heat dissipation over the coming years. In the desktop system design space, the tendency has been to minimize system enclosure size while maximizing performance, which in turn leads to high power densities in future generation systems. The current thermal solutions used today consist of advanced heat sink designs and heat pipe designs with forced air cooling to cool high power processors. However, these techniques are already reaching their limits to handle high heat flux, and there is a strong need for development of more efficient cooling systems which are scalable to handle the high heat flux generated by the future products. To meet this challenge, there has been research in academia and in industry to explore alternative methods for extracting heat from high-density power sources in electronic systems. This talk will discuss the issues surrounding device cooling, from the transistor level to the system level, and describe system-level solutions being developed for desktop computer applications developed in our group at Stanford University.
International Journal of High Speed Electronics and Systems, 2006
Recent trends in processor power for the next generation devices point clearly to significant inc... more Recent trends in processor power for the next generation devices point clearly to significant increase in processor heat dissipation over the coming years. In the desktop system design space, the tendency has been to minimize system enclosure size while maximizing performance, which in turn leads to high power densities in future generation systems. The current thermal solutions used today consist of advanced heat sink designs and heat pipe designs with forced air cooling to cool high power processors. However, these techniques are already reaching their limits to handle high heat flux, and there is a strong need for development of more efficient cooling systems which are scalable to handle the high heat flux generated by the future products. To meet this challenge, there has been research in academia and in industry to explore alternative methods for extracting heat from high-density power sources in electronic systems. This talk will discuss the issues surrounding device cooling, from the transistor level to the system level, and describe system-level solutions being developed for desktop computer applications developed in our group at Stanford University.
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Papers by Sanjiv Sinha