2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV)
In recent technologies of Electronics applications, Adder is an important source of any devices s... more In recent technologies of Electronics applications, Adder is an important source of any devices such as DSP, VLSI applications. For which, many electronics application devices used the high speed adders namely Parallel Prefix Adder (PPA). Generally, PP Adders have less delay due to its less waiting time of carry for next addition. But the area consumption is more, in which the performance of the adders will decrease for higher order bits’ addition. This paper is to design an area efficient Kogge Stone PPA which performs the parallel arithmetic operations in CMOS applications and analysed the design based on the parameters like area and power individually. The proposed area efficient KSA design used the Pass Transistor Logic (PTL) and analysed the performance of particular design. The Performance results of PTL with PP-KSA design used the reduce number of MOS devices which yields less area consumption compared to basic design of 4-bit PP-KSA. Entire analysis results of these designs can be done in Microwind CMOS tool.
2017 IEEE International Conference on Circuits and Systems (ICCS), 2017
The role of digital adder in Digital system design using Very Large Scale Integration (VLSI) tech... more The role of digital adder in Digital system design using Very Large Scale Integration (VLSI) technique is very important. The performance of low power VLSI based adder design has been affected by Propagation Delay (PD) problem. A survey of adder's availability for low power VLSI design with minimum PD is done with the help of Parallel prefix adders design. This paper clarified about the design and analysis of various Parallel Prefix Adders (PPA) also compared with the performance of these adders on the aspects of area, delay and power. From the investigation results it clears that the Kogge stone adder (KSA) is superior for the delay process, so the speed of the addition is automatically increased. But it takes more power consumption and area.
international journal of engineering trends and technology, 2015
Noise reduction of speech signals is a key challenge problem in speech enhancement, speech recogn... more Noise reduction of speech signals is a key challenge problem in speech enhancement, speech recognition and speech communication applications, etc. It has attracted a considerable amount of research attention over past several decades. The most widely used method is optimal linear filtering method, which achieves clean speech estimate by passing the noise observation through an optimal filter or transformation. Most common problem in speech processing is the effect of interference noise in speech signals, Interference noise masks of the speech signal and reduces its Intelligibility. It is necessary to remove the noise from the speech signals to get the clear understanding of the information that the speech signal contains. Normally, LMS adaptive filter is used for the process of noise removal in the speech signals. The Direct Form LMS adaptive filter is the most popular and most widely used adaptive filter, not only because of its simplicity but also because of its satisfactory conve...
International Journal of Scientific & Technology Research, 2020
In digital processing techniques, the fundamental operations such as sum, division can be carried... more In digital processing techniques, the fundamental operations such as sum, division can be carried out by several categories of adders with different sum times, requirements of area and power consumption. The Residue number system (RNS) based processor mainly used in many digital signal processing applications which mainly consists of reverse conversion (residue to binary) process. This paper analyzed the design o Reverse Converter which based upon the RNS of DSP applications with various adders and algorithms. Now a days a role of RNS based processor is an essential in many signal processing applications. From the analysis, it shows that the Hybrid modulo Parallel-prefix Excess-one adder (HMPE) with Chinese Remainder Theorem (CRT) Reverse Converter design is well suitable for better performance on the aspects of delay and area.
This paper presents a fast and unconditionally stable maximum power point tracking scheme with hi... more This paper presents a fast and unconditionally stable maximum power point tracking scheme with high tracking efficiency is proposed for photovoltaic generators. Due to the variation of atmospheric conditions, the photovoltaic (PV) cells do not supply the stable maximum power usually. Some days PV cells provide low power, at that situation the low power can be boosted up to maximum power and applied for special applications.The MPPT power stage is implemented by means of a DC-DC converter and at the front end, most commonly pulse width modulation (PWM) is used. The processing analysis is controlled by ARM-11 (Raspberry pi), and the power result is viewed by any monitor display (T.V or laptop). Thus the system gives the stable maximum power for any situations even for supplying low power from photovoltaic generators. The system uses the ARM11 (Advanced Risc Machine) processor with an RTOS. The Real-Time Linux (RT Linux) operating system is used in this maximum power point tracking met...
Advances in Science, Technology and Engineering Systems Journal, 2019
The basic processes like addition, subtraction can be done using various types of binary adders w... more The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.
To produce the MUX inputs, the CSLA adder design can be accompanied with a CLA structure and achi... more To produce the MUX inputs, the CSLA adder design can be accompanied with a CLA structure and achieve better performance known as PPA. In today's world of technology, the VLSI chips trustseriously on fast and consistent arithmetic processes, in that the PPA is very suitable for implementation [18]. Brent Kung Adder (BKA), Kogge Stone Adder (KSA), Ladner Fischer Adder (LFA), and Hans Carlson Adder (HCA) are the some available types of PPA. PPA involves with three basic stages like Preprocessing stage, Carry generation stage and Postprocessing stages. The pre-processing part generates Propagate (P) and Generate (G) bits as same as CLA equation [2]. In the carry generation stage, carriers are generated by parallel form and include with carry operator that contains two AND gates and one OR gate. Here P and G signals are considered as in-between signals which are measured by equations (1) & (2), P (i:k) =P(i:j). P (j-1: k) (1) G(i:k) =G(i:j) +(G(j-1:k). P (i:j)) (2) The final stage as the Post-processing stagewhich is used to calculate the sum of input bits and output carry which is same for all adders. The various types of PPA are discussed in following section.
2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV)
In recent technologies of Electronics applications, Adder is an important source of any devices s... more In recent technologies of Electronics applications, Adder is an important source of any devices such as DSP, VLSI applications. For which, many electronics application devices used the high speed adders namely Parallel Prefix Adder (PPA). Generally, PP Adders have less delay due to its less waiting time of carry for next addition. But the area consumption is more, in which the performance of the adders will decrease for higher order bits’ addition. This paper is to design an area efficient Kogge Stone PPA which performs the parallel arithmetic operations in CMOS applications and analysed the design based on the parameters like area and power individually. The proposed area efficient KSA design used the Pass Transistor Logic (PTL) and analysed the performance of particular design. The Performance results of PTL with PP-KSA design used the reduce number of MOS devices which yields less area consumption compared to basic design of 4-bit PP-KSA. Entire analysis results of these designs can be done in Microwind CMOS tool.
2017 IEEE International Conference on Circuits and Systems (ICCS), 2017
The role of digital adder in Digital system design using Very Large Scale Integration (VLSI) tech... more The role of digital adder in Digital system design using Very Large Scale Integration (VLSI) technique is very important. The performance of low power VLSI based adder design has been affected by Propagation Delay (PD) problem. A survey of adder's availability for low power VLSI design with minimum PD is done with the help of Parallel prefix adders design. This paper clarified about the design and analysis of various Parallel Prefix Adders (PPA) also compared with the performance of these adders on the aspects of area, delay and power. From the investigation results it clears that the Kogge stone adder (KSA) is superior for the delay process, so the speed of the addition is automatically increased. But it takes more power consumption and area.
international journal of engineering trends and technology, 2015
Noise reduction of speech signals is a key challenge problem in speech enhancement, speech recogn... more Noise reduction of speech signals is a key challenge problem in speech enhancement, speech recognition and speech communication applications, etc. It has attracted a considerable amount of research attention over past several decades. The most widely used method is optimal linear filtering method, which achieves clean speech estimate by passing the noise observation through an optimal filter or transformation. Most common problem in speech processing is the effect of interference noise in speech signals, Interference noise masks of the speech signal and reduces its Intelligibility. It is necessary to remove the noise from the speech signals to get the clear understanding of the information that the speech signal contains. Normally, LMS adaptive filter is used for the process of noise removal in the speech signals. The Direct Form LMS adaptive filter is the most popular and most widely used adaptive filter, not only because of its simplicity but also because of its satisfactory conve...
International Journal of Scientific & Technology Research, 2020
In digital processing techniques, the fundamental operations such as sum, division can be carried... more In digital processing techniques, the fundamental operations such as sum, division can be carried out by several categories of adders with different sum times, requirements of area and power consumption. The Residue number system (RNS) based processor mainly used in many digital signal processing applications which mainly consists of reverse conversion (residue to binary) process. This paper analyzed the design o Reverse Converter which based upon the RNS of DSP applications with various adders and algorithms. Now a days a role of RNS based processor is an essential in many signal processing applications. From the analysis, it shows that the Hybrid modulo Parallel-prefix Excess-one adder (HMPE) with Chinese Remainder Theorem (CRT) Reverse Converter design is well suitable for better performance on the aspects of delay and area.
This paper presents a fast and unconditionally stable maximum power point tracking scheme with hi... more This paper presents a fast and unconditionally stable maximum power point tracking scheme with high tracking efficiency is proposed for photovoltaic generators. Due to the variation of atmospheric conditions, the photovoltaic (PV) cells do not supply the stable maximum power usually. Some days PV cells provide low power, at that situation the low power can be boosted up to maximum power and applied for special applications.The MPPT power stage is implemented by means of a DC-DC converter and at the front end, most commonly pulse width modulation (PWM) is used. The processing analysis is controlled by ARM-11 (Raspberry pi), and the power result is viewed by any monitor display (T.V or laptop). Thus the system gives the stable maximum power for any situations even for supplying low power from photovoltaic generators. The system uses the ARM11 (Advanced Risc Machine) processor with an RTOS. The Real-Time Linux (RT Linux) operating system is used in this maximum power point tracking met...
Advances in Science, Technology and Engineering Systems Journal, 2019
The basic processes like addition, subtraction can be done using various types of binary adders w... more The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.
To produce the MUX inputs, the CSLA adder design can be accompanied with a CLA structure and achi... more To produce the MUX inputs, the CSLA adder design can be accompanied with a CLA structure and achieve better performance known as PPA. In today's world of technology, the VLSI chips trustseriously on fast and consistent arithmetic processes, in that the PPA is very suitable for implementation [18]. Brent Kung Adder (BKA), Kogge Stone Adder (KSA), Ladner Fischer Adder (LFA), and Hans Carlson Adder (HCA) are the some available types of PPA. PPA involves with three basic stages like Preprocessing stage, Carry generation stage and Postprocessing stages. The pre-processing part generates Propagate (P) and Generate (G) bits as same as CLA equation [2]. In the carry generation stage, carriers are generated by parallel form and include with carry operator that contains two AND gates and one OR gate. Here P and G signals are considered as in-between signals which are measured by equations (1) & (2), P (i:k) =P(i:j). P (j-1: k) (1) G(i:k) =G(i:j) +(G(j-1:k). P (i:j)) (2) The final stage as the Post-processing stagewhich is used to calculate the sum of input bits and output carry which is same for all adders. The various types of PPA are discussed in following section.
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