2006 IEEE International Conference on Evolutionary Computation, 2006
The design of a complex embedded system is dominated by the definition of an optimal architecture... more The design of a complex embedded system is dominated by the definition of an optimal architecture in relation to certain performance indexes. This activity, known as design space exploration (DSE), is a great challenge for the EDA (electronic design automation) community. The enormous size of the design space, in fact, together with the long simulation time required to evaluate each
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005
Page 1. Exploring Design Space of VLIW Architectures Giuseppe Ascia Vincenzo Catania Maurizio Pal... more Page 1. Exploring Design Space of VLIW Architectures Giuseppe Ascia Vincenzo Catania Maurizio Palesi Davide Patti Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy {gascia,vcatania,mpalesi,dpatti}@diit.unict.it Abstract ... Tab. ...
In this paper we show that single photon detectors (SPAD) are capable to be used as material qual... more In this paper we show that single photon detectors (SPAD) are capable to be used as material quality probes in the range from 10 13 to 10 10 defects/cm 3 . We have fabricated Spads with differences in the n + formation: some of them have been doped by ion implantation and some others by in situ doped poly-Si deposition. Having found different dark counting behaviour, we introduce a model that aims to give a quantitative analysis for the defects.
2010 IEEE International Symposium on Industrial Electronics, 2010
Reliability and compactness are two aspects often fighting among themselves when speaking about p... more Reliability and compactness are two aspects often fighting among themselves when speaking about power electronics, but, indeed, they are the keys for the success of any new circuit or device. Reliability, in particular, is the word of the moment, powering the development of advanced device design techniques having the reliability as a major goal. Endurance tests is the traditional way to evaluate the reliability of power devices. However, they are very time expensive, requiring even months of uninterrupted testing. An interesting alternative is the estimation of the reliability of a device through a suitable model, but, no standard techniques have been developed up to now to accomplish this task. A possible approach is followed in this paper to assess the reliability of Power MOSFETs driving inductive loads, by exploitation of a dynamic analysis of the temperature distribution over the source metal. Coupling such an analysis with a reliability model, carried out from the Coffin-Manson law, the device life time is estimated. Such a procedure is then used to assess the reliability of Power MOS devices tasked to control the brake pump in a modern vehicle. The consistence of the reliability estimation is confirmed by comparison with results of endurance tests. The described approach can be usefully applied to a large set of applications of MOSFETs in the automotive field.
2010 IEEE Energy Conversion Congress and Exposition, 2010
The on state resistance of power MOSFETs tasked to perform repetitive avalanche operations is sub... more The on state resistance of power MOSFETs tasked to perform repetitive avalanche operations is subject to modifications caused by the growth of voids and cracks in the source metallization. Endurance tests are the traditional way to monitor these changes in order to assess the device reliability. However, they are very time expensive, requiring even months of uninterrupted operations. An interesting alternative consists in the assessment of the reliability through a suitable model, but no standard techniques have been developed up to now to accomplish this task. A possible approach is followed in this paper exploiting a dynamic analysis of the temperature distribution over the source metal. Coupling the thermodynamic analysis with a reliability model, carried out from the Coffin-Manson law, the device degradation over the time can be estimated and the level of reliability as well. The consistence of the obtained reliability prediction is confirmed by comparison with results of endurance tests. The described approach can be usefully applied to assess the reliability of MOSFETs in a large set of applications in the automotive field.
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a soluti... more The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW), in particular, have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case ASIP specialization may require not only manipulation of the instruction-set but also tuning of the architectural parameters of the processor and the memory subsystem . Setting the parameters so as to optimize certain metrics requires the use of efficient Design Space Exploration (DSE) strategies, simulation tools and accurate estimation models operating at a high level of abstraction. In this paper we present a framework for evaluation, in terms of performance, cost and power consumption, of a system based on a parameterized VLIW microprocessor together with the memory hierarchy. Further, the framework implements a number of multi-objective DSE strategies to obtain Pareto-optimal configurations for the system.
Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the ... more Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness of these processors depends on the ability of compilers to provide sufficient instructionlevel parallelism (ILP) in program codes. The main factor limiting the possibility of obtaining high ILP levels is the presence of conditional branches, which prevent a VLIW compiler from scheduling instructions belonging to different paths in parallel. Hyperblock formation is the main compiling technique to solve this limit affecting ILP, transforming the code in such a way as to eliminate conditional branches. The paper presents an analysis of the effect of this technique, not only from the well-known perspective of performance gain but from that of power dissipation and energy consumption. The effect of hyperblock formation on these magnitudes is presented for a set of typical embedded multimedia applications, introducing the non-trivial problems this aggressive ILP technique causes in the increasingly widespread scenario of multiobjective performance, energy and power optimization.
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this p... more Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of Neighbors-on-Path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the Odd-Even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption.
... general (it is fully customized to design space exploration of a memory hierarchy) the ... sp... more ... general (it is fully customized to design space exploration of a memory hierarchy) the ... space pruning is achieved by using Pareto-based evolutionary computing techniques which allow ... problem of the complexity of the evaluation phase we propose using approximators based on ...
... In this paper we present a case study of design space ex-ploration of a complex highly ... an... more ... In this paper we present a case study of design space ex-ploration of a complex highly ... an environment that not only allows to evaluate any instance of a platform in terms of area,performance ... total of 4 cores per blade) equipped with 8GB of DDR2 and a 73GB SATA HD, linked ...
Today's computer systems have become unbelievably com... more Today's computer systems have become unbelievably complex. Nowadays register-level design is an overwhelming task, especially in the embedded system area where the time-to-market is very short. Platform based design shifts the challenge on how to tune parametric platforms to achieve the best performance at the smallest cost. This task, called multi-objective design space exploration, requires accurate strategies because the design
Web browsers are a common platform for delivering cross-platform applications. However, they curr... more Web browsers are a common platform for delivering cross-platform applications. However, they currently fail to provide consistent access control for security and privacy sensitive JavaScript APIs, such as geolocation and local storage. This problem is exacerbated by new HTML5 APIs and the increasing number of personal devices people own and use. In this paper we present the webinos platform which aims to provide a single, cross-device policy system for web applications on a wide range of web-enabled devices including TVs, smartphones, in-car systems and PCs. webinos solves the existing deficiencies in web authorisation by introducing the concept of a personal zone, the set of all devices and services owned by a particular user. All devices in this zone can synchronize their access control policies through interoperable middleware and can create flexible rules which may refer to an individual user, device or the entire zone. We provide details of the architecture and explain how our experience during design highlighted several conceptual challenges.
The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of... more The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multiobjective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Paretooptimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.
One of the most important bottleneck in the overall design flow of a complex embedded system is d... more One of the most important bottleneck in the overall design flow of a complex embedded system is due to the simulation. Simulation occurs at every phase of the design flow. In this paper we focus on system level design proposing a novel approach to speed up the evaluation of a system configuration. The approach, which uses a fuzzy system as
2006 IEEE International Conference on Evolutionary Computation, 2006
The design of a complex embedded system is dominated by the definition of an optimal architecture... more The design of a complex embedded system is dominated by the definition of an optimal architecture in relation to certain performance indexes. This activity, known as design space exploration (DSE), is a great challenge for the EDA (electronic design automation) community. The enormous size of the design space, in fact, together with the long simulation time required to evaluate each
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005
Page 1. Exploring Design Space of VLIW Architectures Giuseppe Ascia Vincenzo Catania Maurizio Pal... more Page 1. Exploring Design Space of VLIW Architectures Giuseppe Ascia Vincenzo Catania Maurizio Palesi Davide Patti Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy {gascia,vcatania,mpalesi,dpatti}@diit.unict.it Abstract ... Tab. ...
In this paper we show that single photon detectors (SPAD) are capable to be used as material qual... more In this paper we show that single photon detectors (SPAD) are capable to be used as material quality probes in the range from 10 13 to 10 10 defects/cm 3 . We have fabricated Spads with differences in the n + formation: some of them have been doped by ion implantation and some others by in situ doped poly-Si deposition. Having found different dark counting behaviour, we introduce a model that aims to give a quantitative analysis for the defects.
2010 IEEE International Symposium on Industrial Electronics, 2010
Reliability and compactness are two aspects often fighting among themselves when speaking about p... more Reliability and compactness are two aspects often fighting among themselves when speaking about power electronics, but, indeed, they are the keys for the success of any new circuit or device. Reliability, in particular, is the word of the moment, powering the development of advanced device design techniques having the reliability as a major goal. Endurance tests is the traditional way to evaluate the reliability of power devices. However, they are very time expensive, requiring even months of uninterrupted testing. An interesting alternative is the estimation of the reliability of a device through a suitable model, but, no standard techniques have been developed up to now to accomplish this task. A possible approach is followed in this paper to assess the reliability of Power MOSFETs driving inductive loads, by exploitation of a dynamic analysis of the temperature distribution over the source metal. Coupling such an analysis with a reliability model, carried out from the Coffin-Manson law, the device life time is estimated. Such a procedure is then used to assess the reliability of Power MOS devices tasked to control the brake pump in a modern vehicle. The consistence of the reliability estimation is confirmed by comparison with results of endurance tests. The described approach can be usefully applied to a large set of applications of MOSFETs in the automotive field.
2010 IEEE Energy Conversion Congress and Exposition, 2010
The on state resistance of power MOSFETs tasked to perform repetitive avalanche operations is sub... more The on state resistance of power MOSFETs tasked to perform repetitive avalanche operations is subject to modifications caused by the growth of voids and cracks in the source metallization. Endurance tests are the traditional way to monitor these changes in order to assess the device reliability. However, they are very time expensive, requiring even months of uninterrupted operations. An interesting alternative consists in the assessment of the reliability through a suitable model, but no standard techniques have been developed up to now to accomplish this task. A possible approach is followed in this paper exploiting a dynamic analysis of the temperature distribution over the source metal. Coupling the thermodynamic analysis with a reliability model, carried out from the Coffin-Manson law, the device degradation over the time can be estimated and the level of reliability as well. The consistence of the obtained reliability prediction is confirmed by comparison with results of endurance tests. The described approach can be usefully applied to assess the reliability of MOSFETs in a large set of applications in the automotive field.
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a soluti... more The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW), in particular, have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case ASIP specialization may require not only manipulation of the instruction-set but also tuning of the architectural parameters of the processor and the memory subsystem . Setting the parameters so as to optimize certain metrics requires the use of efficient Design Space Exploration (DSE) strategies, simulation tools and accurate estimation models operating at a high level of abstraction. In this paper we present a framework for evaluation, in terms of performance, cost and power consumption, of a system based on a parameterized VLIW microprocessor together with the memory hierarchy. Further, the framework implements a number of multi-objective DSE strategies to obtain Pareto-optimal configurations for the system.
Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the ... more Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness of these processors depends on the ability of compilers to provide sufficient instructionlevel parallelism (ILP) in program codes. The main factor limiting the possibility of obtaining high ILP levels is the presence of conditional branches, which prevent a VLIW compiler from scheduling instructions belonging to different paths in parallel. Hyperblock formation is the main compiling technique to solve this limit affecting ILP, transforming the code in such a way as to eliminate conditional branches. The paper presents an analysis of the effect of this technique, not only from the well-known perspective of performance gain but from that of power dissipation and energy consumption. The effect of hyperblock formation on these magnitudes is presented for a set of typical embedded multimedia applications, introducing the non-trivial problems this aggressive ILP technique causes in the increasingly widespread scenario of multiobjective performance, energy and power optimization.
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this p... more Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of Neighbors-on-Path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the Odd-Even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption.
... general (it is fully customized to design space exploration of a memory hierarchy) the ... sp... more ... general (it is fully customized to design space exploration of a memory hierarchy) the ... space pruning is achieved by using Pareto-based evolutionary computing techniques which allow ... problem of the complexity of the evaluation phase we propose using approximators based on ...
... In this paper we present a case study of design space ex-ploration of a complex highly ... an... more ... In this paper we present a case study of design space ex-ploration of a complex highly ... an environment that not only allows to evaluate any instance of a platform in terms of area,performance ... total of 4 cores per blade) equipped with 8GB of DDR2 and a 73GB SATA HD, linked ...
Today's computer systems have become unbelievably com... more Today's computer systems have become unbelievably complex. Nowadays register-level design is an overwhelming task, especially in the embedded system area where the time-to-market is very short. Platform based design shifts the challenge on how to tune parametric platforms to achieve the best performance at the smallest cost. This task, called multi-objective design space exploration, requires accurate strategies because the design
Web browsers are a common platform for delivering cross-platform applications. However, they curr... more Web browsers are a common platform for delivering cross-platform applications. However, they currently fail to provide consistent access control for security and privacy sensitive JavaScript APIs, such as geolocation and local storage. This problem is exacerbated by new HTML5 APIs and the increasing number of personal devices people own and use. In this paper we present the webinos platform which aims to provide a single, cross-device policy system for web applications on a wide range of web-enabled devices including TVs, smartphones, in-car systems and PCs. webinos solves the existing deficiencies in web authorisation by introducing the concept of a personal zone, the set of all devices and services owned by a particular user. All devices in this zone can synchronize their access control policies through interoperable middleware and can create flexible rules which may refer to an individual user, device or the entire zone. We provide details of the architecture and explain how our experience during design highlighted several conceptual challenges.
The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of... more The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multiobjective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Paretooptimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.
One of the most important bottleneck in the overall design flow of a complex embedded system is d... more One of the most important bottleneck in the overall design flow of a complex embedded system is due to the simulation. Simulation occurs at every phase of the design flow. In this paper we focus on system level design proposing a novel approach to speed up the evaluation of a system configuration. The approach, which uses a fuzzy system as
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