Es wird eine Einrichtung zum Prufen einer digitalen Schaltung vorgeschlagen, bei der eine erste i... more Es wird eine Einrichtung zum Prufen einer digitalen Schaltung vorgeschlagen, bei der eine erste in die zu prufende Schaltung (2) eingebaute Prufschaltung (3) BILBO A (Built-In Logic Block Observation) zum Erzeugen eines Pseudo-Zufalls-Prufmusters, eine zweite in die zu prufende Schaltung (2) eingebaute Prufschaltung (5) BILBO B zum Analysieren eines Parallel-Eingangswortes, ein in die zu prufende Schaltung (2) eingebauter Decoder (6) und zumindest ein Zustandsanzeiger (7 oder 8) zum Anzeigen des Zustandes «Fehlerfrei" oder des Zustandes «Fehlerhaft" der zu prufenden Schaltung (2) vorgesehen sind.
1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989
... 2.0, JTAG Technical Committee, March 30, 1988 (3) A Proposed Standard Test BUS And BoundarySc... more ... 2.0, JTAG Technical Committee, March 30, 1988 (3) A Proposed Standard Test BUS And BoundaryScan Architecture, Lee Whetsel, WESCON'88 Session Record 13 (4) Boundary Scan -- A User's Point Of View, Ulrich Ludemann and Heinz Vogt, WESCON'88 Session Record ...
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 1988
A description is given of the concept and issues of design for testability for mixed analog-digit... more A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions
IEEE Proceedings of the Custom Integrated Circuits Conference, 1990
The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are present... more The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are presented. Testing RAMs requires a test strategy different from that used to test random logic because RAMs have more fault types. In general, for a given fault model such as the stuck-at one/zero model, testing a RAM requires more test vectors than testing a random-logic circuit of the same number of equivalent gates. Embedded RAMs are even more difficult to test because of the limited access to the original nodes of the RAMs
Es wird eine Einrichtung zum Prufen einer digitalen Schaltung vorgeschlagen, bei der eine erste i... more Es wird eine Einrichtung zum Prufen einer digitalen Schaltung vorgeschlagen, bei der eine erste in die zu prufende Schaltung (2) eingebaute Prufschaltung (3) BILBO A (Built-In Logic Block Observation) zum Erzeugen eines Pseudo-Zufalls-Prufmusters, eine zweite in die zu prufende Schaltung (2) eingebaute Prufschaltung (5) BILBO B zum Analysieren eines Parallel-Eingangswortes, ein in die zu prufende Schaltung (2) eingebauter Decoder (6) und zumindest ein Zustandsanzeiger (7 oder 8) zum Anzeigen des Zustandes «Fehlerfrei" oder des Zustandes «Fehlerhaft" der zu prufenden Schaltung (2) vorgesehen sind.
1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989
... 2.0, JTAG Technical Committee, March 30, 1988 (3) A Proposed Standard Test BUS And BoundarySc... more ... 2.0, JTAG Technical Committee, March 30, 1988 (3) A Proposed Standard Test BUS And BoundaryScan Architecture, Lee Whetsel, WESCON'88 Session Record 13 (4) Boundary Scan -- A User's Point Of View, Ulrich Ludemann and Heinz Vogt, WESCON'88 Session Record ...
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 1988
A description is given of the concept and issues of design for testability for mixed analog-digit... more A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions
IEEE Proceedings of the Custom Integrated Circuits Conference, 1990
The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are present... more The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are presented. Testing RAMs requires a test strategy different from that used to test random logic because RAMs have more fault types. In general, for a given fault model such as the stuck-at one/zero model, testing a RAM requires more test vectors than testing a random-logic circuit of the same number of equivalent gates. Embedded RAMs are even more difficult to test because of the limited access to the original nodes of the RAMs
Uploads
Papers by Patrick Fasang