ABSTRACT Chapter 4 presents various dedicated methods that support variability handling in the de... more ABSTRACT Chapter 4 presents various dedicated methods that support variability handling in the design process. Using these methods, the designer can analyze the effect of variations on his design and identify possible improvements.
Performance Management is the key factor to successfully persist in the semiconductor market. In ... more Performance Management is the key factor to successfully persist in the semiconductor market. In this paper an approach for analyzing and evaluating semiconductor design projects is presented. The design process is transformed into a task graph to better analyze and optimize its dependencies. Optimization objectives can be time as well as costs. Key Performance Indicators (KPIs) are defined and classified into the main areas finance, resources, process and technical output to appraise the project.
Virtual prototyping of AMS systems is a key concern in modern SoC verification. Achieving first-t... more Virtual prototyping of AMS systems is a key concern in modern SoC verification. Achieving first-time right designs is a challenging task: Every relevant functional and non-functional property has to be examined throughout the complete design process. Many faulty designs have been verified carefully before tape out but are still missing at least one low-level effect which arises from interaction between one or more system components. Since these extra-functional effects are often neglected on system level, the design cannot be rectified in early design stages or verified before fabrication. We introduce a method to determine system acceptance regions tackling this challenge: We include extra-functional effects into the system models, and we investigate their behavior with parallel simulations in combination with an accelerated analog simulation scheme. The accelerated simulation approach is based on local linearizations of nonlinear circuits, which result in piecewise-linear systems. High-level simulation speed-up is achieved by avoiding numerical integration and using parallel computing. This approach is fully automated requiring only a circuit netlist. To reduce the overall number of simulations, we use an adaptive sampling algorithm for exploring systems acceptance regions which indicate feasible and critical operating conditions of the AMS system.
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020
We present the first work on the automated generation of reachset conformant models for analog ci... more We present the first work on the automated generation of reachset conformant models for analog circuits. Our approach applies reachset conformant synthesis to add non-determinism to piecewiselinear circuit models so that they then enclose all possible behaviors of the real system. Since piecewiselinear models are hybrid, we introduce the first reachset conformant synthesis algorithm for hybrid system models. Furthermore we present a novel technique to compute the required non-determinism. The effectiveness of our approach is demonstrated on a real analog circuit. Since the resulting models enclose all measurements, they can be used for formal verification.
Process Variations and Probabilistic Integrated Circuit Design, 2011
In industrial design flows, library standard cells today are represented in Nonlinear Delay Model... more In industrial design flows, library standard cells today are represented in Nonlinear Delay Models (NLDMs). This model and its limitations are described here. It has been recognized since a number of years that this model appears to be increasingly incapable of dealing ...
Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar ... more Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the func- tionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic tran- sistors have to be included into a postlayout simulation. A method- ology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behav- ior and accuracy of the model has been found. Index Terms—Bipolar transistors, nonlinearities, numerical stability, power system simulation, semiconductor device modeling.
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017
This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasi... more This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
2018 17th International Symposium on Parallel and Distributed Computing (ISPDC), 2018
The growing complexity of VLSI designs demands for continuous performance improvement of Electron... more The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020
In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of... more In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.
This paper tackles the analog and mixed-signal modeling for verification challenges. It proposes ... more This paper tackles the analog and mixed-signal modeling for verification challenges. It proposes an adjustable automated modeling approach, which provides set-valued models with reduced overapproximation. The models reliably enclose parameter variations and modeling errors. The reduced overapproximation is obtained by computing the intersecting set of models with intervals and affine forms. The nonlinear circuit examples show a reduced overapproximation up to 86%.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
Formal methods are a promising alternative to simulation-based verification of mixed-signal syste... more Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today's analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This article shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multi-run simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phaselocked loop (PLL) of an IEEE 802.15.4 transceiver system.
2014 6th Computer Science and Electronic Engineering Conference (CEEC), 2014
Machine learning algorithms have recently been used successfully to generate behavioral models of... more Machine learning algorithms have recently been used successfully to generate behavioral models of analog circuits. We take this approach one step further and include parameter variations directly into models using specialized interval arithmetics. We developed a new support vector machine algorithm which estimates functions with interval-valued parameters. We applied this approach to modeling non-linear, static transfer functions of analog circuits with parameter variations and successfully simulated these models using a custom-built simulator.
2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
In 3D-Floorplanning even more than in 2D-Floorplanning new objectives, e.g. temperature, TSV-Plan... more In 3D-Floorplanning even more than in 2D-Floorplanning new objectives, e.g. temperature, TSV-Planning or IR-Drop are considered. This increases the complexity of the problem formulation and, therefore, of the optimization algorithm, dramatically. Apart from some analytical approaches, simulated annealing based algorithms (SA) are widely used for 3D-Floorplanning. To increase the solution quality of classical SA, a common approach is to adapt the selection operations, improving local search. While previous work proposes selection operations which consider mostly one single design issue (e.g. temperature or fixed-outline), we propose a comprehensive multiobjective floorplan optimization methodology (smart SA) which is capable of efficiently considering several objectives and constraints (area, wirelength, fixed-outline, maximum number of TSVs and maximum temperature) at the same time. For the objectives and constraints we present simplified analysis models. Experimental results show that our extended SA algorithm outperforms the classical one and finds valid solutions where classical SA fails.
Proceedings of the Eighth EAI International Conference on Simulation Tools and Techniques, 2015
The behaviour of systems is determined by various parameters. Due to several reasons like e. g. m... more The behaviour of systems is determined by various parameters. Due to several reasons like e. g. manufacturing tolerances these parameters can have some uncertainties. Corner Case and Monte Carlo simulations are well known approaches to handle uncertain systems. They sample the corners and random points of the parameter space, respectively. Both require many runs and do not guarantee the inclusion of the worst case. As alternatives, range based approaches can be used. They model parameter uncertainties as ranges. The simulation outputs are ranges which include all possible results created by the parameter uncertainties. One type of range arithmetic is the affine arithmetic, which allows to maintain linear correlations to avoid over-approximation. An equation solver based on affine arithmetic has been proposed earlier. Unlike many other range based approaches it can solve implicit non-linear equations. This is necessary for analog circuit simulation. For large uncertainties the solver suffers from convergence problems. To overcome these problems it is possible to split the parameter ranges, calculate the solutions separately and merge them again. For higher dimensional systems this leads to excessive runtimes as each parameter is split. To minimize the additional runtime several split and merge strategies are proposed and compared using two analog circuit examples.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming ... more Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.
In nanometer technologies the importance of opens as yield detractors considerably increases. Thi... more In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges
ABSTRACT Chapter 4 presents various dedicated methods that support variability handling in the de... more ABSTRACT Chapter 4 presents various dedicated methods that support variability handling in the design process. Using these methods, the designer can analyze the effect of variations on his design and identify possible improvements.
Performance Management is the key factor to successfully persist in the semiconductor market. In ... more Performance Management is the key factor to successfully persist in the semiconductor market. In this paper an approach for analyzing and evaluating semiconductor design projects is presented. The design process is transformed into a task graph to better analyze and optimize its dependencies. Optimization objectives can be time as well as costs. Key Performance Indicators (KPIs) are defined and classified into the main areas finance, resources, process and technical output to appraise the project.
Virtual prototyping of AMS systems is a key concern in modern SoC verification. Achieving first-t... more Virtual prototyping of AMS systems is a key concern in modern SoC verification. Achieving first-time right designs is a challenging task: Every relevant functional and non-functional property has to be examined throughout the complete design process. Many faulty designs have been verified carefully before tape out but are still missing at least one low-level effect which arises from interaction between one or more system components. Since these extra-functional effects are often neglected on system level, the design cannot be rectified in early design stages or verified before fabrication. We introduce a method to determine system acceptance regions tackling this challenge: We include extra-functional effects into the system models, and we investigate their behavior with parallel simulations in combination with an accelerated analog simulation scheme. The accelerated simulation approach is based on local linearizations of nonlinear circuits, which result in piecewise-linear systems. High-level simulation speed-up is achieved by avoiding numerical integration and using parallel computing. This approach is fully automated requiring only a circuit netlist. To reduce the overall number of simulations, we use an adaptive sampling algorithm for exploring systems acceptance regions which indicate feasible and critical operating conditions of the AMS system.
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020
We present the first work on the automated generation of reachset conformant models for analog ci... more We present the first work on the automated generation of reachset conformant models for analog circuits. Our approach applies reachset conformant synthesis to add non-determinism to piecewiselinear circuit models so that they then enclose all possible behaviors of the real system. Since piecewiselinear models are hybrid, we introduce the first reachset conformant synthesis algorithm for hybrid system models. Furthermore we present a novel technique to compute the required non-determinism. The effectiveness of our approach is demonstrated on a real analog circuit. Since the resulting models enclose all measurements, they can be used for formal verification.
Process Variations and Probabilistic Integrated Circuit Design, 2011
In industrial design flows, library standard cells today are represented in Nonlinear Delay Model... more In industrial design flows, library standard cells today are represented in Nonlinear Delay Models (NLDMs). This model and its limitations are described here. It has been recognized since a number of years that this model appears to be increasingly incapable of dealing ...
Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar ... more Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the func- tionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic tran- sistors have to be included into a postlayout simulation. A method- ology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behav- ior and accuracy of the model has been found. Index Terms—Bipolar transistors, nonlinearities, numerical stability, power system simulation, semiconductor device modeling.
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017
This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasi... more This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
2018 17th International Symposium on Parallel and Distributed Computing (ISPDC), 2018
The growing complexity of VLSI designs demands for continuous performance improvement of Electron... more The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020
In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of... more In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.
This paper tackles the analog and mixed-signal modeling for verification challenges. It proposes ... more This paper tackles the analog and mixed-signal modeling for verification challenges. It proposes an adjustable automated modeling approach, which provides set-valued models with reduced overapproximation. The models reliably enclose parameter variations and modeling errors. The reduced overapproximation is obtained by computing the intersecting set of models with intervals and affine forms. The nonlinear circuit examples show a reduced overapproximation up to 86%.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
Formal methods are a promising alternative to simulation-based verification of mixed-signal syste... more Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today's analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This article shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multi-run simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phaselocked loop (PLL) of an IEEE 802.15.4 transceiver system.
2014 6th Computer Science and Electronic Engineering Conference (CEEC), 2014
Machine learning algorithms have recently been used successfully to generate behavioral models of... more Machine learning algorithms have recently been used successfully to generate behavioral models of analog circuits. We take this approach one step further and include parameter variations directly into models using specialized interval arithmetics. We developed a new support vector machine algorithm which estimates functions with interval-valued parameters. We applied this approach to modeling non-linear, static transfer functions of analog circuits with parameter variations and successfully simulated these models using a custom-built simulator.
2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
In 3D-Floorplanning even more than in 2D-Floorplanning new objectives, e.g. temperature, TSV-Plan... more In 3D-Floorplanning even more than in 2D-Floorplanning new objectives, e.g. temperature, TSV-Planning or IR-Drop are considered. This increases the complexity of the problem formulation and, therefore, of the optimization algorithm, dramatically. Apart from some analytical approaches, simulated annealing based algorithms (SA) are widely used for 3D-Floorplanning. To increase the solution quality of classical SA, a common approach is to adapt the selection operations, improving local search. While previous work proposes selection operations which consider mostly one single design issue (e.g. temperature or fixed-outline), we propose a comprehensive multiobjective floorplan optimization methodology (smart SA) which is capable of efficiently considering several objectives and constraints (area, wirelength, fixed-outline, maximum number of TSVs and maximum temperature) at the same time. For the objectives and constraints we present simplified analysis models. Experimental results show that our extended SA algorithm outperforms the classical one and finds valid solutions where classical SA fails.
Proceedings of the Eighth EAI International Conference on Simulation Tools and Techniques, 2015
The behaviour of systems is determined by various parameters. Due to several reasons like e. g. m... more The behaviour of systems is determined by various parameters. Due to several reasons like e. g. manufacturing tolerances these parameters can have some uncertainties. Corner Case and Monte Carlo simulations are well known approaches to handle uncertain systems. They sample the corners and random points of the parameter space, respectively. Both require many runs and do not guarantee the inclusion of the worst case. As alternatives, range based approaches can be used. They model parameter uncertainties as ranges. The simulation outputs are ranges which include all possible results created by the parameter uncertainties. One type of range arithmetic is the affine arithmetic, which allows to maintain linear correlations to avoid over-approximation. An equation solver based on affine arithmetic has been proposed earlier. Unlike many other range based approaches it can solve implicit non-linear equations. This is necessary for analog circuit simulation. For large uncertainties the solver suffers from convergence problems. To overcome these problems it is possible to split the parameter ranges, calculate the solutions separately and merge them again. For higher dimensional systems this leads to excessive runtimes as each parameter is split. To minimize the additional runtime several split and merge strategies are proposed and compared using two analog circuit examples.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming ... more Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.
In nanometer technologies the importance of opens as yield detractors considerably increases. Thi... more In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges
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Papers by Markus Olbrich