Modeling Lateral Parasitic Transistors in

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the func- tionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic tran- sistors have to be included into a postlayout simulation. A method- ology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behav- ior and accuracy of the model has been found. Index Terms—Bipolar transistors, nonlinearities, numerical stability, power system simulation, semiconductor device modeling.