Papers by Marcos Carneiro
Anais do Encontro Nacional de Engenharia de Produção, 2021
Neste artigo é apresentada uma revisão bibliográfica sobre a otimização do projeto de redes de fi... more Neste artigo é apresentada uma revisão bibliográfica sobre a otimização do projeto de redes de fibra óptica e o avanço nos algoritmos metaheurísticos utilizados para este propósito de 1990 a 2020. Essa otimização requer o tratamento de problemas técnicos e econômicos como, a alocação de recursos de enlaces e nós, a proteção de falhas, limitações orçamentárias, dentre outros. Devido à natureza desses desafios, as metaheurísticas bio-inspiradas baseadas em inteligência de enxame tem sido um conjunto de técnicas promissoras para o fornecimento de soluções para problemas complexos de otimização combinatória, conforme os dados apresentados nesta revisão. O artigo apresenta o estado-da-arte com relação ao uso de algoritmos bioinspirados para a otimização do projeto de rede de fibra óptica, as principais complexidades ao implementar esse tipo de metodologia, as lacunas e oportunidades de pesquisa nesse contexto.
2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE), 2019
Parkinson’s Disease (PD) is a neurodegenerative disorder that affects, among other things, the ga... more Parkinson’s Disease (PD) is a neurodegenerative disorder that affects, among other things, the gait rhythm. This paper presents an automatic method to identify PD subjects from healthy subjects using information derived from a time series of stride intervals, swing intervals, stance intervals and double support intervals of stride-to-stride measures of footfall contact times using force-sensitive resistors. In our approach, we propose the use of machine learning based classifiers along with features based on metrics of fluctuation magnitude and fluctuation dynamics, obtained from a detrended fluctuation analysis. We evaluate and compare performance of five state-of-the-art classification methods according to their accuracies: Support Vector Machine (SVM), K-Nearest Neighbor (KNN), Naive Bayes (NB), Linear Discriminant Analysis (LDA) and Decision Tree (DT). Our experiments were carried out on a publicly available data base of gait dynamics in neurodegenerative diseases. The results show an average accuracy of 96.8%, representing an improvement compared to other results in the literature. Therefore, the proposed approach presents a path towards an automated, non-invasive and low-cost diagnosis of Parkinson’s Disease.
2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI), 2019
This paper describes the synthesis method and implementation in 65-nm CMOS technology of a compac... more This paper describes the synthesis method and implementation in 65-nm CMOS technology of a compact analog phase-shifter (PS) dedicated to 24/28 GHz applications. This PS delivers a phase shift continuously tunable from 0 to 55° and is particularly suited for on-chip or in-package phased-array antenna. The proposed topology, which is based on an all-pass circuit that includes coupled microstrip lines and varactors as tunable components is intrinsically compact and shows an interesting phase-range vs capacitance-variation ratio.
Anais do 10. Congresso Brasileiro de Inteligência Computacional, 2016
Resumo-Um otimizador genético robusto baseado na transformada de incerteza e no Algoritmo Genétic... more Resumo-Um otimizador genético robusto baseado na transformada de incerteza e no Algoritmo Genético de Seleção por Não-dominação-IIé apresentado. O algoritmo proporciona redução significativa do custo computacional se comparado com o método de Monte Carlo. A transformada de incerteza permite a determinação das incertezas do desempenho do circuito a partir das incertezas dos componentes, proporcionando uma busca guiada pela robustez. Além da economia do custo computacional apresentada, outro resultado são as diversas opções de circuitos oferecidas ao projetista através da busca de múltiplos objetivos. O amplificador de potência Doherty foi utilizado como estudo de caso.
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 2013
ABSTRACT A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS techn... more ABSTRACT A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. The amplifier has 23.4 dBm output power and both PAE peaks have the same level in 25%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce losses and correctly balance their behavior.
2015 IEEE International Wireless Symposium (IWS 2015), 2015
This paper deals with the implementation of a RF Doherty Power Amplifier (DPA) with the objective... more This paper deals with the implementation of a RF Doherty Power Amplifier (DPA) with the objective of improving the average efficiency. This technique is an interesting way to provide efficient PA for high PAPR signal of more recent standards of communications. The Doherty principle is applied to a 2.5GHz fully integrated PA on a CMOS 65nm technology. The DPA exhibits 23.4dBm output power, 15dB of power gain and 24.7% of PAE on a 7 dB power range. The die size is 2.89mm2. To fulfill high data rates, wide-band behavior is a big challenge. Hence the wideband behavior of integrated DPA is also investigated.
2014 9th European Microwave Integrated Circuit Conference, 2014
Impedance network topology optimization method is proposed for saving die area and increasing per... more Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, Pout of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the Pout in 2dB.
Ce papier presente un amplificateur de puissance (PA) de type Doherty totalement integre en techn... more Ce papier presente un amplificateur de puissance (PA) de type Doherty totalement integre en technologie 65 nm CMOS de STMicroelectronics. Pour une frequence de 2,535 GHz, il presente une puissance maximale Poutmax de 22dBm. Les deux sous-amplificateurs constituant le PA Doherty, ainsi que les reseaux d'entree et de sortie ont ete optimises pour obtenir une PAE constante et egale a 20% sur une plage de recul en puissance de 8dB. En comparaison avec un amplificateur classe AB, le rendement est augmente de 12% a 8dB de plage de recul en puissance.
2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
ABSTRACT A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS techn... more ABSTRACT A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. Electromagnetic models of each layout path were included in the optimization to dimension circuit components regarding parasitics of an accurate model. The method increased the PAE level in 6% through a constant 8.75 dB backoff range and increased in 2 dB the output power. The amplifier has an output power of 24 dBm, the first PAE peak is 26% and the second one 27%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce the number of inductances and to correctly balance active-loadpull effect. Comparisons were done between schematic, post-layout and electromagnetic simulation.
Analog Integrated Circuits and Signal Processing, 2014
Design methodology and measurements results are presented for a Doherty power amplifier (DPA) ful... more Design methodology and measurements results are presented for a Doherty power amplifier (DPA) fully integrated with its input/output network matching and choke inductances in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 to 2.6 GHz show constant PAE performance starting in 20 % level up to 24 % with a maximum output power of 23.4 dBm. The circuit is fully described with all components values and layout details for further reproduction. Performance graphs showing the active load-pull effect, sub-amplifiers behavior and constant PAE prove that it is a real DPA with all effects as known by the theory. The circuit is composed by only lumped components, each subamplifier has cascode topology and their input/output networks are optimized to save die area and to produce a constant PAE.
IEEE Latin America Transactions, 2011
The PLC Programmable Logic Controller programming is a time consuming task and it needs specific ... more The PLC Programmable Logic Controller programming is a time consuming task and it needs specific knowledge about the programming language and especially of the PLC, which makes it an expensive work by the need of a high qualified professional. This paper proposes a technique to create programs to PLCs by means of Genetic Programming (GP). As objective function, a group of scenarios were used, which represents the behavior of the automated ambient and that can be defined in an intuitive way without previous knowledge of the PLC or a programming language. The technique showed to be generic for many problems and efficient in finding fast different solutions. With an after-processing analysis, the results indicated parameters configuration that optimizes the genetic search.
Ce papier decrit la realisation d’un dephaseur analogique ultra-compact reglable en continu de 0 ... more Ce papier decrit la realisation d’un dephaseur analogique ultra-compact reglable en continu de 0 a 45° sur une bande de 25 a 30 GHz en technologie CMOS 65nm. La compacite du design final est obtenue a partir d’une topologie initiale de dephaseur presentant un rapport plage de variation de phase/compacite interessant combinee a une technologie de lignes couplees CPW a ondes lentes, reduisant encore la longueur d’un rapport 2 a 3. De plus, l’introduction de coupure dans les rubans flottants permet d’obtenir une souplesse de conception supplementaire exploitee ici pour elargir la gamme d’impedances paires et impaires realisables. Finalement, une comparaison avec des approches classiques (microruban et CPW) est proposee.
New Circuits and …, 2011
A robust genetic circuit optimizer using Unscented Transform and Non-dominated Sorting Genetic Al... more A robust genetic circuit optimizer using Unscented Transform and Non-dominated Sorting Genetic Algorithm-II is presented. The algorithm provides significant decrease in computational cost compared to Monte Carlo method. This transform permits the circuit performance uncertainties determination from components uncertainties, thus, a search through robustness can be done. Results shows reduced computational costs, the many possibilities provided to circuit designer by the multi-objective search and assumptions that can be done in a Doherty power amplifier study with the optimizer.
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Papers by Marcos Carneiro