Papers by Kumar Narasimhan Dwarakanath
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior o... more Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture misbehaviors beyond logic faults is then illustrated using many examples of varying degree of complexity. In particular, the ability of fault tuples to modulate fault controllability and observability is examined. Finally, it is described how fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics.
We i n troduce a new fault representation mechanism for digital circuits based on fault tuples. A... more We i n troduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17 reduction of average CPU time is achiev ed when performing sim ulation on all fault t ypes simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.
International Test Conference, 2003. Proceedings. ITC 2003., 2003
Multiple-detect test sets have been shown to be ef- fective in lowering defect level. Other resea... more Multiple-detect test sets have been shown to be ef- fective in lowering defect level. Other researchers have noted that observing the effects of a defect can be con- trolled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a de- fect's inherent, unknown nature. As a result, test sets that sensitize every signal line multiple
Proceedings of the 43rd …, 2006
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to suppo... more In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-...
Test Conference, 2000. …, 2000
A test generation tool for combinational circuits called FATGEN has been developed based on the n... more A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults.
International Test Conference, 2002
Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increa... more Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself. At the same time, key diagnostic tasks that include defect localization are still solved using primitive models of the IC's defects. This paper explores the use of "fault tuples" in diagnosis. Fault tuples
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Papers by Kumar Narasimhan Dwarakanath