In this paper we propose a small-signal model of the semiconductor equations accounting for time-... more In this paper we propose a small-signal model of the semiconductor equations accounting for time-dependent carrier storage within generation-recombination centers. Such an effect is expected to be essential for the correct prediction of capacitance-frequency curves in devices containing a large amount of deep traps, such as stressed MOSFET’s and polycrystalline-silicon thin-film transistors. The model has been implemented in HFIELDS and shown to provide results in qualitative good agreement with experimental data available from the literature.
2014 44th European Solid State Device Research Conference (ESSDERC), 2014
A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs ... more A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs is developed and compared with full-quantum simulation results. It will be shown that the pure analytical solution perfectly matches results at high V DS. However, a coupling with the numerical solution of the 1D Poisson equation in the radial direction is necessary at low V DS , in order to properly account for the charge density in equilibrium with the drain contact. With such an approach we are able to correctly predict the potential profile for both the linear and saturation regimes.
EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015
We compare band-structure calculations obtained with modeling approaches hierarchically spanning ... more We compare band-structure calculations obtained with modeling approaches hierarchically spanning from density functional theory to tight-binding, k·p and non-parabolic effective mass descriptions. We consider III-V quantum-wells with thickness ranging from 3nm to 10nm. Comparison with experiments for unstrained and strained InGaAs quantum-wells is also reported.
2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011
In this work we investigate by numerical simulation the achievable performance of a steep-slope n... more In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs- InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/µm at a supply voltage of 400 mV.
2009 Proceedings of the European Solid State Device Research Conference, 2009
In this work we present an investigation on the program, retention and erase mechanisms of cylind... more In this work we present an investigation on the program, retention and erase mechanisms of cylindrical gate-all-around charge-trapping memories. The numerical model accounts for tunnel injection of electrons and holes from the channel and the gate into the silicon nitride layer; for carrier transport, capture and emission in the nitride, and allows for both planar and cylindrical geometries. Simulations of
In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect tra... more In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with nonideal edges.
ABSTRACT Effect of transverse quantization on the broken vs. staggered band lineup of InAs/AlxGa1... more ABSTRACT Effect of transverse quantization on the broken vs. staggered band lineup of InAs/AlxGa1-xSb TFETs is investigated, showing that cross-sections up to 10nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an “optimal” design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μA/μm.
We show that a ballistic quantum transport model based on the effective mass approximation can fa... more We show that a ballistic quantum transport model based on the effective mass approximation can fairly well describe the I-V characteristics of armchair graphene nanoribbon FETs at all bias conditions, including regimes dominated by direct or band-to-band tunneling, provided first-order non-parabolic corrections be included in the simulation. This is achieved by means of an energy (position) dependent effective mass. The analysis is supported by comparisons with an atomistic tight-binding model.
In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FE... more In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current-voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schrödinger-Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.
... Muller, GK Wachutka, W. Fichtner, SISDEP 91 Proc., p. 141, 1991. 3 R. Stratton, Phys. Rev., v... more ... Muller, GK Wachutka, W. Fichtner, SISDEP 91 Proc., p. 141, 1991. 3 R. Stratton, Phys. Rev., vol. 126, n.6, p. 2002, 1962. 4 K. Huang, Statistical mechanics, p. 8, Wiley, 1963. 5 P. Ciampolini, A. Pierantoni, G. Baccarani, SISDEP 91 Proc.p. 149, 1991. 6 S. Middelhoek, SA Audet ...
The ultimate scaling limits of p-in carbon-nanotube field-effect transistors (CNT-FETs) are inves... more The ultimate scaling limits of p-in carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum-mechanical transport within the nonequilibrium Green's function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the lowoperating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-in CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.
... G. Baccarani is on leave from the University of Eologna, Bologna, town Heights, NY 10598. Ita... more ... G. Baccarani is on leave from the University of Eologna, Bologna, town Heights, NY 10598. Italy. A. SAI-HALASZ, SENIOR MEMBER, IEEE 1 Fig. ... 1981. See also: "MOS Device and Technolog) Constraints in VLSI". fEEE Trans. on Electron Dev., ED-29, pp. 567-573, April 1982. ...
An analytical formulation of the threshold voltage variance induced by random dopant fluctuations... more An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large V DS , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.
In this paper we propose a small-signal model of the semiconductor equations accounting for time-... more In this paper we propose a small-signal model of the semiconductor equations accounting for time-dependent carrier storage within generation-recombination centers. Such an effect is expected to be essential for the correct prediction of capacitance-frequency curves in devices containing a large amount of deep traps, such as stressed MOSFET’s and polycrystalline-silicon thin-film transistors. The model has been implemented in HFIELDS and shown to provide results in qualitative good agreement with experimental data available from the literature.
2014 44th European Solid State Device Research Conference (ESSDERC), 2014
A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs ... more A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs is developed and compared with full-quantum simulation results. It will be shown that the pure analytical solution perfectly matches results at high V DS. However, a coupling with the numerical solution of the 1D Poisson equation in the radial direction is necessary at low V DS , in order to properly account for the charge density in equilibrium with the drain contact. With such an approach we are able to correctly predict the potential profile for both the linear and saturation regimes.
EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015
We compare band-structure calculations obtained with modeling approaches hierarchically spanning ... more We compare band-structure calculations obtained with modeling approaches hierarchically spanning from density functional theory to tight-binding, k·p and non-parabolic effective mass descriptions. We consider III-V quantum-wells with thickness ranging from 3nm to 10nm. Comparison with experiments for unstrained and strained InGaAs quantum-wells is also reported.
2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011
In this work we investigate by numerical simulation the achievable performance of a steep-slope n... more In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs- InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/µm at a supply voltage of 400 mV.
2009 Proceedings of the European Solid State Device Research Conference, 2009
In this work we present an investigation on the program, retention and erase mechanisms of cylind... more In this work we present an investigation on the program, retention and erase mechanisms of cylindrical gate-all-around charge-trapping memories. The numerical model accounts for tunnel injection of electrons and holes from the channel and the gate into the silicon nitride layer; for carrier transport, capture and emission in the nitride, and allows for both planar and cylindrical geometries. Simulations of
In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect tra... more In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with nonideal edges.
ABSTRACT Effect of transverse quantization on the broken vs. staggered band lineup of InAs/AlxGa1... more ABSTRACT Effect of transverse quantization on the broken vs. staggered band lineup of InAs/AlxGa1-xSb TFETs is investigated, showing that cross-sections up to 10nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an “optimal” design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μA/μm.
We show that a ballistic quantum transport model based on the effective mass approximation can fa... more We show that a ballistic quantum transport model based on the effective mass approximation can fairly well describe the I-V characteristics of armchair graphene nanoribbon FETs at all bias conditions, including regimes dominated by direct or band-to-band tunneling, provided first-order non-parabolic corrections be included in the simulation. This is achieved by means of an energy (position) dependent effective mass. The analysis is supported by comparisons with an atomistic tight-binding model.
In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FE... more In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current-voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schrödinger-Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.
... Muller, GK Wachutka, W. Fichtner, SISDEP 91 Proc., p. 141, 1991. 3 R. Stratton, Phys. Rev., v... more ... Muller, GK Wachutka, W. Fichtner, SISDEP 91 Proc., p. 141, 1991. 3 R. Stratton, Phys. Rev., vol. 126, n.6, p. 2002, 1962. 4 K. Huang, Statistical mechanics, p. 8, Wiley, 1963. 5 P. Ciampolini, A. Pierantoni, G. Baccarani, SISDEP 91 Proc.p. 149, 1991. 6 S. Middelhoek, SA Audet ...
The ultimate scaling limits of p-in carbon-nanotube field-effect transistors (CNT-FETs) are inves... more The ultimate scaling limits of p-in carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum-mechanical transport within the nonequilibrium Green's function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the lowoperating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-in CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.
... G. Baccarani is on leave from the University of Eologna, Bologna, town Heights, NY 10598. Ita... more ... G. Baccarani is on leave from the University of Eologna, Bologna, town Heights, NY 10598. Italy. A. SAI-HALASZ, SENIOR MEMBER, IEEE 1 Fig. ... 1981. See also: "MOS Device and Technolog) Constraints in VLSI". fEEE Trans. on Electron Dev., ED-29, pp. 567-573, April 1982. ...
An analytical formulation of the threshold voltage variance induced by random dopant fluctuations... more An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large V DS , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.
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Papers by G. Baccarani