ABSTRACT With the availability of modern application specific integrated circuit (ASIC) design to... more ABSTRACT With the availability of modern application specific integrated circuit (ASIC) design tools, simulation packages, and low-cost commercial silicon foundry processes, it is becoming increasingly easy for any laboratory, or small company, to develop a custom ASIC. For stimulation, as well as recording, chips that perform specialized functions can be designed, fabricated, and tested within a time period of 2-3 months. In many cases, the desired functionality can only be obtained by using VLSI design methods. Despite this increase in ASIC functionality, as related to neural engineering applications, there exists no common interface protocol for communicating with, and controlling, neural engineering ASICs. This would be analogous to each company that manufactures PC-based systems to have no common method of communication, e.g. USB, GBIB, RS-232, etc. While it might seem elusive, we propose the specification and development of a universal interface protocol for neural engineering ASICs. We have named this interface, NeuroTalk.
ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device struc... more ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device structures sensitive to ultraviolet radiation. These UV-sensitive structures can be integrated with detection and signal-conditioning circuitry to make monolithic smart UV sensors. Test results for fabricated sensing circuits are presented, including experimental results for a monolithic UV dosimeter.
2006 International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
With the availability of modern application specific integrated circuit (ASIC) design tools, simu... more With the availability of modern application specific integrated circuit (ASIC) design tools, simulation packages, and low-cost commercial silicon foundry processes, it is becoming increasingly easy for any laboratory, or small company, to develop a custom ASIC. For stimulation, as well as recording, chips that perform specialized functions can be designed, fabricated, and tested within a time period of 2-3 months. In many cases, the desired functionality can only be obtained by using VLSI design methods. Despite this increase in ASIC functionality, as related to neural engineering applications, there exists no common interface protocol for communicating with, and controlling, neural engineering ASICs. This would be analogous to each company that manufactures PC-based systems to have no common method of communication, e.g. USB, GBIB, RS-232, etc. While it might seem elusive, we propose the specification and development of a universal interface protocol for neural engineering ASICs. We have named this interface, NeuroTalk.
2006 International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
We present a monolithic microelectronic multichannel amplifier designed to facilitate measurement... more We present a monolithic microelectronic multichannel amplifier designed to facilitate measurements from multi-electrode arrays. A single silicon chip includes sixteen electrode amplifiers, along with interface and control circuitry to allow data collection through a compact 4-wire interface.
2008 IEEE Biomedical Circuits and Systems Conference, 2008
As a component of the RP2009 project, the IMES system has emerged as a strong candidate for extra... more As a component of the RP2009 project, the IMES system has emerged as a strong candidate for extracting naturally-occurring control signals to be used for providing functional control of an upper body artificial limb. In earlier publications, we described various elements of this system as they were being researched and developed. Presently, the system has matured to a level for
We describe an analog VLSI implementation of a multi-dimensional gradient estimation and descent ... more We describe an analog VLSI implementation of a multi-dimensional gradient estimation and descent technique for minimizing an onchip scalar function f(). The implementation uses noise injection and multiplicative correlation to estimate derivatives, as in [Anderson, Kerns 92]. One intended application of this technique is setting circuit parameters on-chip automatically, rather than manually [Kirk 91]. Gradient descent optimization may be used to adjust synapse weights for a backpropagation or other on-chip learning implementation. The approach combines the features of continuous multi-dimensional gradient descent and the potential for an annealing style of optimization. We present data measured from our analog VLSI implementation.
ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device struc... more ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device structures sensitive to ultraviolet radiation. These UV-sensitive structures can be integrated with detection and signal-conditioning circuitry to make monolithic smart UV sensors. Test results for fabricated sensing circuits are presented, including experimental results for a monolithic UV dosimeter.
ABSTRACT With the availability of modern application specific integrated circuit (ASIC) design to... more ABSTRACT With the availability of modern application specific integrated circuit (ASIC) design tools, simulation packages, and low-cost commercial silicon foundry processes, it is becoming increasingly easy for any laboratory, or small company, to develop a custom ASIC. For stimulation, as well as recording, chips that perform specialized functions can be designed, fabricated, and tested within a time period of 2-3 months. In many cases, the desired functionality can only be obtained by using VLSI design methods. Despite this increase in ASIC functionality, as related to neural engineering applications, there exists no common interface protocol for communicating with, and controlling, neural engineering ASICs. This would be analogous to each company that manufactures PC-based systems to have no common method of communication, e.g. USB, GBIB, RS-232, etc. While it might seem elusive, we propose the specification and development of a universal interface protocol for neural engineering ASICs. We have named this interface, NeuroTalk.
ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device struc... more ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device structures sensitive to ultraviolet radiation. These UV-sensitive structures can be integrated with detection and signal-conditioning circuitry to make monolithic smart UV sensors. Test results for fabricated sensing circuits are presented, including experimental results for a monolithic UV dosimeter.
2006 International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
With the availability of modern application specific integrated circuit (ASIC) design tools, simu... more With the availability of modern application specific integrated circuit (ASIC) design tools, simulation packages, and low-cost commercial silicon foundry processes, it is becoming increasingly easy for any laboratory, or small company, to develop a custom ASIC. For stimulation, as well as recording, chips that perform specialized functions can be designed, fabricated, and tested within a time period of 2-3 months. In many cases, the desired functionality can only be obtained by using VLSI design methods. Despite this increase in ASIC functionality, as related to neural engineering applications, there exists no common interface protocol for communicating with, and controlling, neural engineering ASICs. This would be analogous to each company that manufactures PC-based systems to have no common method of communication, e.g. USB, GBIB, RS-232, etc. While it might seem elusive, we propose the specification and development of a universal interface protocol for neural engineering ASICs. We have named this interface, NeuroTalk.
2006 International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
We present a monolithic microelectronic multichannel amplifier designed to facilitate measurement... more We present a monolithic microelectronic multichannel amplifier designed to facilitate measurements from multi-electrode arrays. A single silicon chip includes sixteen electrode amplifiers, along with interface and control circuitry to allow data collection through a compact 4-wire interface.
2008 IEEE Biomedical Circuits and Systems Conference, 2008
As a component of the RP2009 project, the IMES system has emerged as a strong candidate for extra... more As a component of the RP2009 project, the IMES system has emerged as a strong candidate for extracting naturally-occurring control signals to be used for providing functional control of an upper body artificial limb. In earlier publications, we described various elements of this system as they were being researched and developed. Presently, the system has matured to a level for
We describe an analog VLSI implementation of a multi-dimensional gradient estimation and descent ... more We describe an analog VLSI implementation of a multi-dimensional gradient estimation and descent technique for minimizing an onchip scalar function f(). The implementation uses noise injection and multiplicative correlation to estimate derivatives, as in [Anderson, Kerns 92]. One intended application of this technique is setting circuit parameters on-chip automatically, rather than manually [Kirk 91]. Gradient descent optimization may be used to adjust synapse weights for a backpropagation or other on-chip learning implementation. The approach combines the features of continuous multi-dimensional gradient descent and the potential for an annealing style of optimization. We present data measured from our analog VLSI implementation.
ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device struc... more ABSTRACT Standard silicon CMOS integrated circuit processes allow the fabrication of device structures sensitive to ultraviolet radiation. These UV-sensitive structures can be integrated with detection and signal-conditioning circuitry to make monolithic smart UV sensors. Test results for fabricated sensing circuits are presented, including experimental results for a monolithic UV dosimeter.
Uploads
Papers by Douglas Kerns