Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2011
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardwar... more Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Our proposal leverages a Hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework supports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity.
Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to p... more Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCo...
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 2008
We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapt... more We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on simple hardware accelerators for common software synchronization patterns. We compare the energy efficiency of a range of shared memory benchmarks using both spin-locks and a simple hardware transactional memory. In most cases, transactional memory provides both significantly reduced energy consumption and increased throughput. We also consider applications that employ concurrency patterns based on semaphores, such as pipelines and barriers. We propose and evaluate a novel energy-efficient hardware semaphore construction in which cores spin on local scratchpad memory, reducing the load on the shared bus.
Proceedings of the great lakes symposium on VLSI, 2012
Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random t... more Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by
2007 IEEE International Symposium on Nanoscale Architectures, 2007
Electrical noise will play an incr easingly cr itical role in future nanoscale CMOS circuit opera... more Electrical noise will play an incr easingly cr itical role in future nanoscale CMOS circuit operation characterized by lower supply voltages V DD and smaller device sizes. Both of these downscaling appr oaches r educe the mar gin of immunity to ther mal noise, alpha par ticle strikes, and thr eshold voltage var iations. This paper investigates the noise pr obability distributions for both equilibr ium and non-equilibr ium logic states of advanced CMOS flip-flops oper ated at ultra-low V DD. The theor etical distribution of transition times from one stable oper ation point to the other stable oper ation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs ar e extremely sensitive to thr eshold var iations, r educing aver age failur e time to a few days. M onte Car lo simulations ar e pr ovided to validate the theor etical model and its pr edictions.
And any paradigm shift in applications and architecture will have a profound effect on the design... more And any paradigm shift in applications and architecture will have a profound effect on the design process and tools required. Researchers must emphasize the complementary architectural and system issues involved in deploying these new technologies and push for greater collaboration at all levels: devices, circuits, architecture, and systems. WHAT IS NANOARCHITECTURE? We define nanoarchitecture as the organization of basic computational structures composed of nanoscale devices assembled into a system that computes something useful. Nanoarchitecture will enable radically different computational models, and, due to its potential for large capacity, might also provide superior capabilities in some areas. Since architecture is rarely created in a vacuum, these issues will greatly affect nanoarchitecture development. There are two paths to follow: evolutionary and revolutionary. Evolutionary path Silicon semiconductor technology will continue to shrink. But there's an increasing performance gap between device technology and its ability to deliver per-Although nanoelectronics won't replace CMOS for some time, research is needed now to develop the architectures, methods, and tools to maximally leverage nanoscale devices and terascale capacity. Addressing the complementary architectural and system issues involved requires greater collaboration at all levels.The effective use of nanotechnology will call for total system solutions.
ACM Transactions on Design Automation of Electronic Systems, 2000
This paper presents a novel approach to the problem of optimizing combinational circuits for low ... more This paper presents a novel approach to the problem of optimizing combinational circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than it would at the technology-independent level. After each node's switching activity in the circuit is determined, high-power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and learning is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power. Bes...
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The effects of temperature on delay depend on several parameters, such as cell size, load, supply... more The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-Vt design; in particular, we show how traditional dual-Vt optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). T... more In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). These diagrams extend BDD'sby allowing values from an arbitrary finite domain to be associatedwith the terminal nodes. We present a treatment foundedin boolean algebras and discuss algorithms and results in applicationslike matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADD's to logicsynthesis, formal verification, and testing of digital systems. 1 IntroductionBinary Decision Diagrams (BDD's) ...
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995
When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric an... more When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as the technology reaches the deep sub-micron range, additional eects as the short circuit current, partial voltage swings, transient behavior between clock cycles and leak current are b e c oming more r elevant to achieve an accurate estimation of the consumption. In this paper we present Meiga, an event-driven simulation-based p ower estimator that accounts for power dissipation due to short circuit current, partial swings and transient behavior. Experiments have shown that circuits in the order of several thousands of transistors are simulated i n s e c onds of CPU per input vector.
This paper studies the problem of estimating worst case power dissipation in a sequential circuit... more This paper studies the problem of estimating worst case power dissipation in a sequential circuit. We approach this problem by nding the maximum average weight cycles in a weighted directed g r aph. In order to handle practical sized examples, we use symbolic methods, based o n A lgebraic Decision Diagrams (ADDs), for computing the maximum average length cycles as well as the number of gate transitions in the circuit, which is necessary to construct the weighted directed g r aph.
Soft errors are going to play an increasingly critical role in logic design, as power consumption... more Soft errors are going to play an increasingly critical role in logic design, as power consumption drives CMOS scaling to ever lower supply voltages and device sizes. Both of these downscaling approaches contribute to significantly increased logic signal noise variance. This paper introduces a new methodology for predicting noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS inverters operated at low supply voltage. These distributions are essential to computing the probability of soft errors. The radiation-induced SER is not considered here.
In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequi... more In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequilibrium Green's functions was presented to model the fluctuations in a CMOS flip-flop, which could potentially give rise to logic upsets. In part II, this framework is used to investigate quantitatively the failure in time for end-of-roadmap CMOS devices at the L G = 10 nm length scale as a function of various parameters such as size, temperature, threshold voltage, process-induced threshold variation, and V DD. It is shown quantitatively that process-induced variation and/or use of ultralow V DD make the devices extremely vulnerable to noise. Higher temperatures give rise to higher failure rates through increased thermal fluctuations and through reduced I on /I off ratios, due to an inverse dependence of the subthreshold slope on temperature. The effect of nonlinear voltage-dependent node capacitors are modeled via the use of arbitrary-shaped queues, and the corresponding results are reported.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014
Many classes of applications, especially in the domains of signal and image processing, computer ... more Many classes of applications, especially in the domains of signal and image processing, computer graphics, computer vision, and machine learning, are inherently tolerant to inaccuracies in their underlying computations. This tolerance can be exploited to design approximate circuits that perform within acceptable accuracies but have much lower power consumption and smaller area footprints (and often better run times) than their exact counterparts. In this paper, we propose a new class of automated synthesis methods for generating approximate circuits directly from behavioral-level descriptions. In contrast to previous methods that operate at the Boolean level or use custom modifications, our automated behavioral synthesis method enables a wider range of possible approximations and can operate on arbitrary designs. Our method first creates an abstract synthesis tree (AST) from the input behavioral description, and then applies variant operators to the AST using an iterative stochastic greedy approach to identify the optimal inexact designs in an efficient way. Our method is able to identify the optimal designs that represent the Pareto frontier trade-off between accuracy and power consumption. Our methodology is developed into a tool we call ABACUS, which we integrate with a standard ASIC experimental flow based on industrial tools. We validate our methods on three realistic Verilog-based benchmarks from three different domains-signal processing, computer vision and machine learning. Our tool automatically discovers optimal designs, providing area and power savings of up to 50% while maintaining good accuracy.
As current silicon-based techniques fast approach their practical limits, the investigation of na... more As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
This paper examines the ramifications of using 3D integration technology on the leakage and timin... more This paper examines the ramifications of using 3D integration technology on the leakage and timing variability of integrated circuits. We develop models that estimate the outcome of mapping a 2D design onto a 3D stack from a process variation perspective. We statistically prove and experimentally demonstrate that 3D integration is a useful technique to combat process variations even if the die/wafers layers involved in 3D stacks are integrated blindly without any parametric tests prior to integration. We further show that if individual die parametric testing information is available, then it is possible to drastically reduce the impact of process variations. We develop fast, near optimal integration strategies based on recursive matching techniques. Our results show that 3D integration can reduce the variability in leakage and timing of planar ICs by around 50% without any testing and by more than 90% with additional test requirements.
In this paper, we investigate the use of logic implications for the online detection of intermitt... more In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible-even with only a 10% area overhead.
Proceedings of the First International Workshop on Many-core Embedded Systems - MES '13, 2013
High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, an... more High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, and home entertainment centers, are becoming ubiquitous. Like their general-purpose counterparts, and for many of the same energy-related reasons, embedded systems are turning to multicore architectures. Moreover, as the demand for more compute-intensive capabilities for embedded systems increases, these multicore architectures will evolve into manycore systems for improved performance or performance/area/Watt. These systems are often organized as cluster based Non-Uniform Memory Access (NUMA) architectures that provide the programmer with a shared-memory abstraction, with the cost of sharing memory (in terms of performance, energy, and complexity) varying substantially depending on the locations of the communicating processes. This paper investigates one of the principal challenges presented by these emerging NUMA architectures for embedded systems: providing efficient, energy-effective and convenient mechanisms for synchronization and communication. In this paper, we propose an initial solution based on hardware support for speculative synchronization.
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the sta... more Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the stability margin with respect to thermal noise and raising the probability for thermally-induced soft errors. Given the long time scale of noise-induced soft errors, conventional Monte Carlo simulations cannot be used to predict error rates and alternative approaches are needed. In this paper, the analysis of thermal
Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2011
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardwar... more Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Our proposal leverages a Hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework supports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity.
Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to p... more Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCo...
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 2008
We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapt... more We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on simple hardware accelerators for common software synchronization patterns. We compare the energy efficiency of a range of shared memory benchmarks using both spin-locks and a simple hardware transactional memory. In most cases, transactional memory provides both significantly reduced energy consumption and increased throughput. We also consider applications that employ concurrency patterns based on semaphores, such as pipelines and barriers. We propose and evaluate a novel energy-efficient hardware semaphore construction in which cores spin on local scratchpad memory, reducing the load on the shared bus.
Proceedings of the great lakes symposium on VLSI, 2012
Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random t... more Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by
2007 IEEE International Symposium on Nanoscale Architectures, 2007
Electrical noise will play an incr easingly cr itical role in future nanoscale CMOS circuit opera... more Electrical noise will play an incr easingly cr itical role in future nanoscale CMOS circuit operation characterized by lower supply voltages V DD and smaller device sizes. Both of these downscaling appr oaches r educe the mar gin of immunity to ther mal noise, alpha par ticle strikes, and thr eshold voltage var iations. This paper investigates the noise pr obability distributions for both equilibr ium and non-equilibr ium logic states of advanced CMOS flip-flops oper ated at ultra-low V DD. The theor etical distribution of transition times from one stable oper ation point to the other stable oper ation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs ar e extremely sensitive to thr eshold var iations, r educing aver age failur e time to a few days. M onte Car lo simulations ar e pr ovided to validate the theor etical model and its pr edictions.
And any paradigm shift in applications and architecture will have a profound effect on the design... more And any paradigm shift in applications and architecture will have a profound effect on the design process and tools required. Researchers must emphasize the complementary architectural and system issues involved in deploying these new technologies and push for greater collaboration at all levels: devices, circuits, architecture, and systems. WHAT IS NANOARCHITECTURE? We define nanoarchitecture as the organization of basic computational structures composed of nanoscale devices assembled into a system that computes something useful. Nanoarchitecture will enable radically different computational models, and, due to its potential for large capacity, might also provide superior capabilities in some areas. Since architecture is rarely created in a vacuum, these issues will greatly affect nanoarchitecture development. There are two paths to follow: evolutionary and revolutionary. Evolutionary path Silicon semiconductor technology will continue to shrink. But there's an increasing performance gap between device technology and its ability to deliver per-Although nanoelectronics won't replace CMOS for some time, research is needed now to develop the architectures, methods, and tools to maximally leverage nanoscale devices and terascale capacity. Addressing the complementary architectural and system issues involved requires greater collaboration at all levels.The effective use of nanotechnology will call for total system solutions.
ACM Transactions on Design Automation of Electronic Systems, 2000
This paper presents a novel approach to the problem of optimizing combinational circuits for low ... more This paper presents a novel approach to the problem of optimizing combinational circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than it would at the technology-independent level. After each node's switching activity in the circuit is determined, high-power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and learning is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power. Bes...
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The effects of temperature on delay depend on several parameters, such as cell size, load, supply... more The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-Vt design; in particular, we show how traditional dual-Vt optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). T... more In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). These diagrams extend BDD'sby allowing values from an arbitrary finite domain to be associatedwith the terminal nodes. We present a treatment foundedin boolean algebras and discuss algorithms and results in applicationslike matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADD's to logicsynthesis, formal verification, and testing of digital systems. 1 IntroductionBinary Decision Diagrams (BDD's) ...
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995
When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric an... more When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as the technology reaches the deep sub-micron range, additional eects as the short circuit current, partial voltage swings, transient behavior between clock cycles and leak current are b e c oming more r elevant to achieve an accurate estimation of the consumption. In this paper we present Meiga, an event-driven simulation-based p ower estimator that accounts for power dissipation due to short circuit current, partial swings and transient behavior. Experiments have shown that circuits in the order of several thousands of transistors are simulated i n s e c onds of CPU per input vector.
This paper studies the problem of estimating worst case power dissipation in a sequential circuit... more This paper studies the problem of estimating worst case power dissipation in a sequential circuit. We approach this problem by nding the maximum average weight cycles in a weighted directed g r aph. In order to handle practical sized examples, we use symbolic methods, based o n A lgebraic Decision Diagrams (ADDs), for computing the maximum average length cycles as well as the number of gate transitions in the circuit, which is necessary to construct the weighted directed g r aph.
Soft errors are going to play an increasingly critical role in logic design, as power consumption... more Soft errors are going to play an increasingly critical role in logic design, as power consumption drives CMOS scaling to ever lower supply voltages and device sizes. Both of these downscaling approaches contribute to significantly increased logic signal noise variance. This paper introduces a new methodology for predicting noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS inverters operated at low supply voltage. These distributions are essential to computing the probability of soft errors. The radiation-induced SER is not considered here.
In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequi... more In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequilibrium Green's functions was presented to model the fluctuations in a CMOS flip-flop, which could potentially give rise to logic upsets. In part II, this framework is used to investigate quantitatively the failure in time for end-of-roadmap CMOS devices at the L G = 10 nm length scale as a function of various parameters such as size, temperature, threshold voltage, process-induced threshold variation, and V DD. It is shown quantitatively that process-induced variation and/or use of ultralow V DD make the devices extremely vulnerable to noise. Higher temperatures give rise to higher failure rates through increased thermal fluctuations and through reduced I on /I off ratios, due to an inverse dependence of the subthreshold slope on temperature. The effect of nonlinear voltage-dependent node capacitors are modeled via the use of arbitrary-shaped queues, and the corresponding results are reported.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014
Many classes of applications, especially in the domains of signal and image processing, computer ... more Many classes of applications, especially in the domains of signal and image processing, computer graphics, computer vision, and machine learning, are inherently tolerant to inaccuracies in their underlying computations. This tolerance can be exploited to design approximate circuits that perform within acceptable accuracies but have much lower power consumption and smaller area footprints (and often better run times) than their exact counterparts. In this paper, we propose a new class of automated synthesis methods for generating approximate circuits directly from behavioral-level descriptions. In contrast to previous methods that operate at the Boolean level or use custom modifications, our automated behavioral synthesis method enables a wider range of possible approximations and can operate on arbitrary designs. Our method first creates an abstract synthesis tree (AST) from the input behavioral description, and then applies variant operators to the AST using an iterative stochastic greedy approach to identify the optimal inexact designs in an efficient way. Our method is able to identify the optimal designs that represent the Pareto frontier trade-off between accuracy and power consumption. Our methodology is developed into a tool we call ABACUS, which we integrate with a standard ASIC experimental flow based on industrial tools. We validate our methods on three realistic Verilog-based benchmarks from three different domains-signal processing, computer vision and machine learning. Our tool automatically discovers optimal designs, providing area and power savings of up to 50% while maintaining good accuracy.
As current silicon-based techniques fast approach their practical limits, the investigation of na... more As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
This paper examines the ramifications of using 3D integration technology on the leakage and timin... more This paper examines the ramifications of using 3D integration technology on the leakage and timing variability of integrated circuits. We develop models that estimate the outcome of mapping a 2D design onto a 3D stack from a process variation perspective. We statistically prove and experimentally demonstrate that 3D integration is a useful technique to combat process variations even if the die/wafers layers involved in 3D stacks are integrated blindly without any parametric tests prior to integration. We further show that if individual die parametric testing information is available, then it is possible to drastically reduce the impact of process variations. We develop fast, near optimal integration strategies based on recursive matching techniques. Our results show that 3D integration can reduce the variability in leakage and timing of planar ICs by around 50% without any testing and by more than 90% with additional test requirements.
In this paper, we investigate the use of logic implications for the online detection of intermitt... more In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible-even with only a 10% area overhead.
Proceedings of the First International Workshop on Many-core Embedded Systems - MES '13, 2013
High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, an... more High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, and home entertainment centers, are becoming ubiquitous. Like their general-purpose counterparts, and for many of the same energy-related reasons, embedded systems are turning to multicore architectures. Moreover, as the demand for more compute-intensive capabilities for embedded systems increases, these multicore architectures will evolve into manycore systems for improved performance or performance/area/Watt. These systems are often organized as cluster based Non-Uniform Memory Access (NUMA) architectures that provide the programmer with a shared-memory abstraction, with the cost of sharing memory (in terms of performance, energy, and complexity) varying substantially depending on the locations of the communicating processes. This paper investigates one of the principal challenges presented by these emerging NUMA architectures for embedded systems: providing efficient, energy-effective and convenient mechanisms for synchronization and communication. In this paper, we propose an initial solution based on hardware support for speculative synchronization.
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the sta... more Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the stability margin with respect to thermal noise and raising the probability for thermally-induced soft errors. Given the long time scale of noise-induced soft errors, conventional Monte Carlo simulations cannot be used to predict error rates and alternative approaches are needed. In this paper, the analysis of thermal
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Papers by R. Bahar