WIP

trealla-prolog · Dec 17, 2024 · f72bd38 · f72bd38
1 parent 7410965
commit f72bd38
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/compile.c b/src/compile.c
@@ -48,9 +48,7 @@ static void compile_term(clause *cl, cell **dst, cell **src)
 		return;
 #endif
 	}
-#endif
 
-#if 0
 	if (((*src)->val_off == g_disjunction_s) && ((*src)->arity == 2)) {
 		*src += 1;
 		cell *save_dst1 = *dst;