iverilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Nov 30, 2022
Verilog

JeffDeCola / my-verilog-examples

Star

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

sgherbst / svreal

Star

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

Essenceia / ethernet-physical-layer

Star

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

c fpga rtl verilog ethernet iverilog vpi pcs 10gbase-r 40gbase-r

Updated Jan 2, 2024
Tcl

pytec8800 / pint_iverilog

Star

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

simulation rtl risc-v iverilog

Updated Nov 15, 2021
C++

patrickleboutillier / jcscpu-hw

Star

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

fpga verilog vivado iverilog

Updated Aug 3, 2020
Verilog

yasnakateb / PipelinedARM

Star

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

strongwong / bittyCore_RISC-V

Star

This is a bitty CPU core of risc-v architecture, which is currently under development.

cpu verilog pipeline-processor risc-v iverilog rv32i bittycore

Updated Oct 23, 2020
Verilog

TimRudy / uart-verilog

Star

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface

Updated May 28, 2023
Verilog

johnnycubides / digital-electronic-1-101

Star

fpga verilog yosys iverilog ice40 cyclone-iv

Updated Nov 13, 2024
Verilog

ParimalaS27 / Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

Star

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

verilog prefix icarus-verilog 8bit iverilog parallel-prefixsum prefix-adder ddco