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SoCXin · Dec 9, 2024 · 9247fee · 9247fee
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diff --git a/.editorconfig b/.editorconfig
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+# top-most EditorConfig file
+root = true
+
+# all files
+[*]
+indent_style = tab
+indent_size = 4
+end_of_line = lf
+charset = utf-8
+trim_trailing_whitespace = true
+insert_final_newline = true
diff --git a/.gitattributes b/.gitattributes
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+# Auto detect text files and perform LF normalization
+* text=auto
+# Standard to msysgit
+*.doc   diff=astextplain
+*.DOC   diff=astextplain
+*.docx  diff=astextplain
+*.DOCX  diff=astextplain
+*.dot   diff=astextplain
+*.DOT   diff=astextplain
+*.pdf   diff=astextplain
+*.PDF   diff=astextplain
+*.rtf   diff=astextplain
+*.RTF   diff=astextplain
diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml
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+# These are supported funding model platforms
+
+github: # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2]
+patreon: # Replace with a single Patreon username
+open_collective: # Replace with a single Open Collective username
+ko_fi: qitas
+tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
+community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
+liberapay: # Replace with a single Liberapay username
+issuehunt: # Replace with a single IssueHunt username
+otechie: # Replace with a single Otechie username
+custom: # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2']
diff --git a/.gitignore b/.gitignore
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+*.pyc
+.pio/
+.vscode/
+obj
+.settings
+.template
diff --git a/README.md b/README.md
@@ -1,39 +1,41 @@
-
-# rock-chips
+# [CH32V208](https://doc.soc.xin/CH32V208)
 
-[![sites](docs/mcuyun.png)](http://www.mcuyun.com)
+* [WCH](http://www.wch.cn/)：[RISC-V4C](https://github.com/SoCXin/RISC-V)
+* [L2R2](https://github.com/SoCXin/Level)：144 MHz , [￥5.724](https://item.szlcsc.com/5860926.html)
 
-瑞芯微电子成立于2001年，总部福州，在上海、北京、深圳、杭州均有研发中心，是中国极具创新和务实的集成电路设计公司。
+## [简介](https://github.com/SoCXin/CH32V208/wiki)
 
----
+[CH32V208](https://www.wch.cn/products/CH32V208.html) 系列是基于32位RISC-V内核设计的工业级增强型低功耗通用微控制器，高性能，最高支持144MHz系统主频，低功耗，运行功耗低至45uA/MHz。CH32V208集成双路USB接口，支持USB Host主机及USB Device设备功能，具有1路CAN接口（2.0B主动）、双路OPA运放、4组UART、双路IIC，12位ADC，10路Touchkey等丰富外设资源，同时提供TSSOP20、QFN28、QFN48、LQFP32、LQFP48等多种封装供客户灵活选择。
 
-### RK3399
+### 关键特性
 
-瑞星微最新一代处理器，双Cortex-A72 + 四Cortex-A53大小核CPU结构，包含双ISP像素处理能力高达13MPix/s
+* 144MHz RISC-V4C Core（青稞）
+* 64KB SRAM + 128KB Flash
+* 供电电压：2.5/3.3V，GPIO单元独立供电
+* 多种低功耗模式：睡眠、停止、待机，上/下电复位、可编程电压检测器
+* 低功耗蓝牙5.3
+* 10M以太网控制器（MAC+PHY）
+* 2组运放比较器
+* 16通道12位ADC转换，16路触摸按键TouchKey
+* 5组定时器
+* USB2.0全速主机/设备+设备接口
+* 4个USART接口
+* 1个CAN接口（2.0B主动）
+* 2组IIC接口、2组SPI接口
+* 53个I/O口，可以映射到16外部中断
+* CRC计算单元，96位芯片唯一ID
+* 串行2线调试接口
+* 封装形式：LQFP64M、QFN68、QFN48、QFN28
 
-https://github.com/mcuyun/RK3399.git
+## [收录资源](https://github.com/SoCXin/CH32V208)
 
----
+* [参考资源](src/)
+* [参考文档](docs/)
+* [参考工程](project/)
 
-### RK3326
+## [选型建议](https://github.com/SoCXin)
 
-瑞星微最新一代处理器，四核Cortex-A35，频率最高1.5GHz，包含8M ISP，Mali-G31MP2 GPU
+[CH32V208](https://item.szlcsc.com/5860926.html)和[CH32V203](https://github.com/SoCXin/CH32V203)同属一个系列，相应的开发例程资源都是[CH32V20xEVT_ZIP](https://www.wch.cn/downloads/CH32V20xEVT_ZIP.html)，差异在前者配置了BLE和以太网外设，可以看做是[CH579](https://github.com/SoCXin/CH579)的升级版本。
 
-https://github.com/mcuyun/RK3326.git
-
----
-
-### RK3308
-
-瑞星微最新一代处理器，四核Cortex-A35 频率最高 1.3GHz，包含8路ADC和2路DAC
-
-https://github.com/mcuyun/RK3308.git
-
-
-
----
-
-## 说明
-
-本工程用于索引Nuvoton各个工程
+### [www.SoC.xin](http://www.SoC.Xin)
 
diff --git a/docs/CH32FV2x_V3xRM.PDF b/docs/CH32FV2x_V3xRM.PDF
diff --git a/docs/CH32V208.png b/docs/CH32V208.png
diff --git a/docs/CH32V208DS0.PDF b/docs/CH32V208DS0.PDF
diff --git a/docs/mcuyun.png b/docs/mcuyun.png
diff --git a/index.json b/index.json
@@ -0,0 +1,36 @@
+{
+    "type":"SoC",
+    "name":"CH32V208",
+    "title": "WCH CH32V208 SoC",
+    "description":"WCH RISC-V4C BLE SoC",
+    "Core": {
+        "CoreNum": 1,
+        "Core":"RISC-V",
+        "Fmax":144,
+        "DMIPS": 240,
+        "CoreMark": 400
+    },
+    "manufacturer": {
+        "vendor":"WCH",
+        "homepage":"http://www.wch.cn"
+    },
+    "repository": {
+        "type": "git",
+        "url": "https://github.com/SoCXin/CH32V208.git"
+    },
+    "version":"1.0.0",
+    "series":["CH32V208"],
+    "package":["LQFP64M","QFN68","QFN48","QFN28"],
+    "peripheral": ["BLE","ETH","USB","ADC","UART","SPI","LDO","PWM"],
+    "temp": [-40,85],
+    "volt": [2.5,3.3],
+    "ESD": {
+        "HBM": 4000,
+        "CDM": 500
+    },
+    "keywords": [
+        "RISC-V",
+        "WCH",
+        "BLE","ETH","SDIO","CAN","I2C","RTC","SPI"
+    ]
+}