23
votes
Accepted
What do HDLs compile/synthesize to?
Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file ...
- 134k
19
votes
what is triplication on fpga?
Triplication means (as noted) to make 3 of everything.
It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
- 22.6k
17
votes
What do HDLs compile/synthesize to?
Register Transfer Logic (RTL) is the result of the first translation phase, before it is mapped to the vendor-specific resources, which are not portable between vendors or even between different FPGA ...
- 15.1k
16
votes
Accepted
Are FPGAs for experimentation alone?
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
- 18.2k
11
votes
Accepted
What does the FPGA do with unreferenced I/O pins?
By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be ...
- 23.8k
11
votes
What do HDLs compile/synthesize to?
The physical primitive of an FPGA is a configurable logic block (CLB).
Each logic block is given a dedicated location in memory, so-called configuration memory, that determines how it is configured ...
- 57.3k
10
votes
Accepted
Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
- 703
9
votes
Accepted
in what order does a VHDL program run in an FPGA
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
- 42.4k
6
votes
Help me debug these VHDL errors please
This is not specific to VHDL, but generally here's how to interpret compiler error messages:
Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
- 15.1k
6
votes
Accepted
How do FPGAs implement the inequality operator?
Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces.
Given two numbers, for example 234 and <...
- 20.5k
5
votes
Accepted
Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?
There are different packages for the FPGA. Different packages with different options.
On the 144 pin EP2C8 version of the Altera Cyclone II EP2C5T144C8 Dev Board, pins 26 and 81 are VCCINT and pins ...
- 8,208
5
votes
FPGA maximum frequency : limiting factor
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).
Because your multiplying coefficients are all powers of 2, your multiplies can ...
- 134k
5
votes
Accepted
"expecting endmodule" error, can't understand why?
I see two problems:
The semicolon at the end of the first always line means the whole if structure that follows isn't inside ...
- 134k
5
votes
Accepted
Altera Cyclone V - Linux & FPGA interrupt handling
The HPS bridge is designed to take FPGA interrupts and feed them in to the general interrupt controller (GIC) within the ARM processor. As far as the processor is concerned, interrupts from the FPGA ...
- 70.7k
5
votes
Accepted
Altera Cyclone IV PLL: What limits the available multiplication/division factor values
There are several limits on PLLs. The main one is the VCO output frequency range. You need to pick divider values that will result in an in-range output frequency. Second is the PFD frequency range....
- 41.6k
5
votes
What do HDLs compile/synthesize to?
what bytes go over the write when an FPGA is being programed?
This is less answerable generally, because it is 100% manufacturer-specific and device-specific. Some manufacturers publish datasheets ...
- 6,280
5
votes
Are FPGAs for experimentation alone?
No, FPGAs are used in lots of different products from consumer electronic displays to video / image processing. They are also used in automotive & aerospace vehicles.
Earlier in FPGA's life I ...
- 610
4
votes
Accepted
Replacing an FT2232 chip with a custom microcontroller?
Are these the standard ways of configuring Altera chips? Is there any other popular approach?
Well, at least they're popular. You of course don't have to use an FTDI chip to do JTAG – there's in fact ...
- 100k
4
votes
Accepted
Unexpected behaviour in Altera clock crossing FIFO
I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is ...
- 6,197
4
votes
Accepted
Nios 2 softcore IP
The Altera Stratix part is an FPGA, not a processor. The Nios processor core is implemented on the Stratix FPGA. Soft IP cores are merely high level functional descriptions of a component, the soft ...
- 41.6k
4
votes
Accepted
I2S output in VHDL
As far as I understand, You have chosen synchronous design based on "clock_50".
You have generated two sub-clock from "CLOCK_50" that the clk_div_4 is not used yet. You are listening to GPIO24 as "WS" ...
- 376
4
votes
altera FPGA acting like OR gate when programed as AND gate
Your switches will be active low (i.e. zero when pressed).
Your LEDs will also be active low (i.e. zero will turn them on).
If you invert the inputs and output of an AND gate, you get an OR gate, ...
- 70.7k
4
votes
Raw programming of an Altera FPGA
Surely if you were able to fully comprehend and become knowledgeable of all of the following factors regarding a particular FPGA it would be possible to hand craft programming files for the device.
...
- 57.9k
4
votes
Are FPGAs for experimentation alone?
The cost of going from a design concept to an ASIC is horrendous and easily goes into 100ks$ to 1000ks$ range. Here I am referring to the money we pay to a company to manufactuer our ASICs. Once ...
- 2,311
4
votes
Accepted
Possible to use Segger J-Link with Intel Quartus to flash FPGA?
AFAIK not directly, but through OpenOCD.
You can use quartus_cpf to convert the programming file to SVF format, and then set up the J-Link in OpenOCD.
I have a ...
- 12.8k
4
votes
Accepted
FPGA - synchronise “very close” clock from signal
No two clocks will ever perfectly match. The method of determining the true clock frequency from the data is called "clock recovery".
If you know the nominal bit rate, then one ...
- 12.5k
4
votes
How does Quartus pin planner know about voltage in each I/O bank?
It doesn't know. The Pin Planner is a variant of the more generic Assignment Editor, all it generates are additional constraints on the Fitter.
During compilation, the Fitter will tell you whether it ...
- 12.8k
4
votes
Accepted
3
votes
Altera Cyclone II JTAG after AS Programming
I had the same or very similar problem ("JTAG chain broken"). It seems to solve the problem if I download libudev1:i386 and create a symbolic link
...
- 1,724
Only top scored, non community-wiki answers of a minimum length are eligible