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3 votes
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Why is this not a net antennae? (Altium Designer)

Why would this not be flagged as a net antennae in Altium Designer (25)? This is a GND pour covering all of the bottom layer in my PCB design, and the TH vias (mostly meant to conduct between layers 1 ...
Kenny's user avatar
  • 41
2 votes
3 answers
478 views

PCB layout guidelines Magnetic Sensor

I am using this IC from TI in my design. The layout design guidelines and typical layout is given below. I have some questions regarding the layout guidelines. It says that "Common passive ...
Confused's user avatar
  • 3,061
2 votes
1 answer
47 views

Does "via in a pad" (not via-in-pad) cost extra?

I am trying to add vias to test point pads (40mil round copper pads) on the top layer. I know via-in-pad costs extra due to extra manufacturing steps to fill the vias. But if I add a via in a test ...
Peter's user avatar
  • 81
3 votes
1 answer
135 views

How can I locate via holes for PCB design?

I'm working on a PCB design (Artwork) and looking at the reference PCB layout for the EP4RKU+ (1-to-4 splitter), I see via holes overlapping with the GND pads. However, the PCB design (Artwork) guy ...
Artelec's user avatar
  • 71
2 votes
2 answers
155 views

Is it possible to trace a via on a multilayer PCB board without the schematic diagram?

I have a copper trace on a PCB board, but it terminates in an annular ring. My question is, can I trace the path of the trace? I need to determine if it is connected to ground. Thank you in advance. ...
condor12's user avatar
  • 145
0 votes
0 answers
47 views

EMI performances observed better for stripline routing with pth rather than stripline with blind via

The circuit is: A fast switching driver (Lvth buffer) is transmitting a signal to Leon processor receiver and it also has a series termination. Stackup: top(L1), gnd, sig1(inner lyr3), 2.5V plane, ...
Ankita Sinha's user avatar
0 votes
4 answers
235 views

PCB design: How small can vias be made?

Working with very limited space (In Altium) and need to place vias to make routes between the red solder castellation plates on the top layer to the respective connector pins on the bottom layer, both ...
eutectic_codswallop's user avatar
2 votes
2 answers
160 views

Plating via without chemicals

In my lab we can mill and drill double sided PCBs. Holes are not plated. To create a via we usually use little copper rivets. Electroplating is out of the question because we don’t do any chemicals ...
Leo's user avatar
  • 31
0 votes
2 answers
143 views

Via sizing and parallel vias

How to estimate the via pad diameter? I am using pi*d = trace width I have decided but Saturn PCB Design calculator is giving very lower current value at that diameter. How to decide the via hole ...
Andr7's user avatar
  • 295
4 votes
3 answers
857 views

How to space stitching vias to avoid affecting the power plane?

On a four-layer with the standard sig gnd pwr sig stackup, when flooding top and bottom layers with copper and stitching them to the ground plane, I know the standard rule is lambda/20 spacing for the ...
John Arg's user avatar
  • 259
1 vote
1 answer
128 views

PCB design for Renesas' DA7212 audio codec

I'm designing my very first PCB. I managed to route all my components and I'm stuck at the last footprint - DA7212 from Renesas: Those balls are both incredibly tiny and packed dense. I'd need a ...
Paul Jon's user avatar
0 votes
1 answer
68 views

What is the difference between these vias?

I have marked them with red and purple. What purpose do they serve? P.S. I am new to this, so please help me through this.
courageouslywin's user avatar
4 votes
1 answer
303 views

Deliver high current through vias

There is a demand for a delivery of 3 A through several layers using vias. Presented below in the picture is my PCB manufacturer's abilities regarding vias. A single via can withstand 1.4 A. Are there ...
rocko445's user avatar
2 votes
1 answer
544 views

"Error: Items not allowed (keepout area..)" KiCAD

I have got this erorr. What should i do?
Византија Исток's user avatar
0 votes
1 answer
450 views

KiCAD DRC erorrs

I have problem with this erorrs, but i don't know how to fix it. [![enter image description here][3]][3] But I have this erorrs, what should i do know?
Византија Исток's user avatar
0 votes
0 answers
36 views

Issues with vias on ethernet differential signals in routing [duplicate]

I have ethernet differential signals and a discrete magnetics part. I want to know what issues might arise if I place vias on the differential signals when connecting them between the magnetics and ...
Freshman's user avatar
  • 945
3 votes
1 answer
119 views

Stubs on shielding vias

Shielding vias are used around high speed digital and RF traces. The return current for these kinds of traces primarily flows through the adjacent reference/ground planes. If blind/back-drilled vias ...
aghoras's user avatar
  • 465
3 votes
1 answer
2k views

Kicad 7 - Drill out of range

I had a footprint for a component in Kicad 5. Then i updated to Kicad 7 and I am getting this error: ...
user1584421's user avatar
  • 1,399
2 votes
2 answers
389 views

How are transfer vias used?

I watched a video on via basics by PhilsLab (Video: https://www.youtube.com/watch?v=WPT96w3eLAM), in which he discusses transfer vias. He presents the following picture to explain why you should place ...
Y-E-Quit's user avatar
  • 121
1 vote
1 answer
252 views

Drilled vs micro vias

I understand there are regular PTH vias drilled once all layers are stacked together then plated (e.g. the Thru 1:9 via on the left of the image below) There are also Blind vias which are drilled into ...
MRB's user avatar
  • 421
0 votes
1 answer
54 views

3V3 polygon has a GND vias layer in it

So i dumbly overlooked an error before sending the PCB into production. So my question here is, is there a chance to fix this manually once i get the PCB or is contacting manufacturer is the only ...
narusik's user avatar
  • 13
2 votes
2 answers
190 views

Stitching vias from ground to power a thing? Question on Keysight ADS demo of TI PandaBoard

I'm doing a Keysight ADS demonstration and it seems to show stitching vias between ground and power planes. The PCB is an 8-layer PCB (the Texas Instrument PandaBoard) with two planes, a ground and ...
BipedalJoe's user avatar
0 votes
0 answers
62 views

How does a via stub cause deterministic jitter?

In a PCB, a via stub is the part of a via that is not used to transport the signal between signal layers. A via stub, as far as I know, can damage signal integrity because of signal reflection: at the ...
David Cian's user avatar
9 votes
3 answers
1k views

Why are via stubs not avoided?

Via stubs are defined as the part of a via that is not used for signal transmission. Via stubs cause all sorts of problems, but I just don't understand why they happen in the first place. Can't you ...
David Cian's user avatar
0 votes
2 answers
298 views

Vias for through holes wires such as interconnects & jumpers

I'm going to have some PCB designs fabricated online. I'm quite new to it & I've never actually used KiCad as well for the designing PCBs the whole process. So I have a few questions. I need ...
Tempus Nomen's user avatar
0 votes
1 answer
267 views

How do I provide a PCB manufacturer with via type information (such as "Filling and Capping") from Altium Designer?

I have a PCB design in Altium with all of the IPC 4761 Via Types specified on each via. What are the industry standard ways to provide this information to the manufacturer? I normally export my ...
SSB's user avatar
  • 108
1 vote
2 answers
211 views

Keepout region for Molex SMD connector footprint

I am trying to understand the technical justification to have a keepout region around the 2 large outer pads of a Molex connector (PN# 5055670881). I would like to have more area around these outer ...
Michael Swanson's user avatar
3 votes
0 answers
124 views

How to handle deleted components in PCB layout

I am trying to "update" an Altium project; deleting 3 sheets with all components and adding 2 sheets. I completed the schematics and next step is layout. As I deleted components, I saw so ...
terbus5's user avatar
  • 61
7 votes
2 answers
967 views

What happens if high via current flows in PCB?

If I used a via of 8 mils diameter with 20 um thickness. As per sierra tool calculator it can carry current of 1 A at 10 degree rise in temperature. What happens if the current is more than 1 A? When ...
Selva97's user avatar
  • 543
0 votes
0 answers
55 views

Protecting vias with plated copper with the toner transfer method

With the film photoresist method, the film, if not etched off, can be used to form a protective layer over via to prevent the copper inside from being etched. Is this possible with the toner transfer ...
itisyeetimetoday's user avatar
1 vote
2 answers
355 views

Thermal resistance of via in 1oz vs 2oz PCB

I am planning to do a 0.3 mm dia via array under the exposed pad of a SMD component. 0.3 mm so that the via is small enough that solder mask covers most of vias in the bottom layer so that solder ...
EarthLord's user avatar
  • 619
1 vote
1 answer
428 views

How to remove tenting from specific vias?

I defined a SolderMaskExpansion rule in Altium and with that way all vias are tented. But I want to remove tenting for some of the vias. I mean, I want some vias to be tented and some vias to be non-...
harmonica's user avatar
  • 673
10 votes
6 answers
3k views

How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
Selva97's user avatar
  • 543
2 votes
1 answer
142 views

Are these vias not plated?

I received my first batch of PCB's that were designed with thermal vias of diameter 0.61mm and hole diameter 0.305mm. When I inspect them, it seams that only around 10% of the vias have been coated. ...
K0ICHI's user avatar
  • 497
6 votes
1 answer
2k views

Keep-out area underneath power inductor

I'm designing a DC-DC buck converter and when looking at the inductor's datasheet, I noticed an image showing a restricted area underneath the inductor, between the pads. https://www.we-online.com/...
raaymaan's user avatar
  • 1,364
16 votes
5 answers
5k views

Routing traces to and from a 48 pin microcontroller becoming a mess

I have a 48 pin microcontroller with VCC = 5V. I'm becoming worried that I have the traces too close and all the vias and crossing traces may mess with the signals' integrity. Are there examples and ...
user avatar
3 votes
1 answer
985 views

Matching via sizes to trace widths

Let's say I've determined a trace width (\$t_w\$) for a trace, and now I want to determine the size of a via on that trace. My intuition is that to maintain the same amount of copper as the trace ...
Jason C's user avatar
  • 663
5 votes
5 answers
2k views

What are the risks of having a small annular ring?

I want to increase the hole size of my signal vias on my PCB from 8mil to 12mil since that will save me about $100 getting the boards manufactured. I increased the hole size, but for now, I left the ...
Jay's user avatar
  • 1,207
0 votes
2 answers
1k views

Soldering wire directly to a PCB through hole vias, what is acceptable proximity tolerance?

The wire gauge is 16 AWG. The hole size is 63 mil, and the overall via diameter is 98.5 mil. What is the minimum spacing between two of these for voltage levels of 0-12V and 0-160V circuits? I think I ...
user avatar
0 votes
3 answers
2k views

PCB via size specification

I am designing a PCB in Kicad and I can define any diameter and hole of a via, but when I send it to be manufactured in china (JLCPCB, PCBWAY, etc) they can put any size of via or will it adjust to ...
Ricardo Casimiro's user avatar
0 votes
3 answers
982 views

4 layers PCB VIA and power plane

I’m working on a 4 layer PCB and this is my stackup: 1-TOP (signal) 2-GND (plane) 15-VCC (3V3 plane) 16-BOTTOM (signal) On top layer I have a buck converter with 3V3 and GND output (0.5A max abs. ...
D_A_8's user avatar
  • 57
0 votes
0 answers
111 views

What are the minimum dimensions for a hand soldered castellated hole?

I need to design a pcb with castellated holes, and another with the corresponding pads. I need to solder them by hand, and I cannot find any guidelines on how to design castellated holes for proper ...
JCSB's user avatar
  • 317
0 votes
1 answer
115 views

Can you route multiple returns to the same via?

New to PCB Design and layout. While routing bypass caps, I instinctively give each bypass cap its own via to the ground plane. What would be the disadvantages of having two (or more) bypass caps share ...
Novak's user avatar
  • 1
1 vote
3 answers
341 views

Use vias or point to point connections?

I generally tend to use vias close to the pin to connect my components to GND. I was just wondering what is the right way to make connections when you have two components connecting to say 5V or GND. ...
Hasman404's user avatar
  • 757
0 votes
2 answers
150 views

Rate my first 2-layer board

I would like to hear some comments on my first 2-layer board. Specificaly if I should go with two grounds (one for 12 V, one for 5 V) or just one big ground plane. Another thing is the layout of the ...
ownedcore's user avatar
0 votes
3 answers
4k views

What does the hole size and diameter of a via means in Altium? What do they actually represent?

For my school project, I am designing a small PCB. For routing the signals I need to use a via. There will be around 500mA current flowing through the via. I am using 0.5mm traces to route the signals....
zak3877's user avatar
  • 11
0 votes
1 answer
466 views

Altium 3D View not showing properly and Via placement problem

Can some please tell me how to fix this? I select all 3D views but every time I get transparent board. and when I try to place a via for routing it moves outside of the board. need help.....
Aqib Wahid Butt's user avatar
2 votes
1 answer
139 views

How to correctly create castellations?

The problem: I need to use TSSOP-14 ICs instead of SOIC-14. Have plenty of boards already manufactured and assembled. Deadbug wiring is not an option. I have not found any available converters so I ...
0___________'s user avatar
  • 2,634
1 vote
2 answers
1k views

PCB Design: When having a power plane, should I only be doing vias or also route?

Is it some times relevant to also make the routing between two nodes that are close to each other? Or is it always sufficient to just have vias? The same question for something other than power, such ...
Robin Hellmers's user avatar
2 votes
0 answers
622 views

Multi-layer Via-in-pad with 0.5mm Pitch BGA in KiCad

I am working on a 4 layer board with an 81 pin 0.5mm pitch BGA which effectively requires via-in-pad for dropping down to other layers. Decoupling must be done on the bottom as there is no space for ...
David Black's user avatar