Questions tagged [high-speed]
High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.
372 questions
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ZYNQ XC7Z010-3CLG400E - Can I use SPI MIO to EMIO?
This will be my first attempt to design PCB based on Xilinx Zynq device. The specific part number is XC7Z010-3CLG400E. My main objective is to learn how to design high speed peripherals including DDR3,...
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PRBS for testing high speed interfaces
Many times you see datasheets showcasing high speed transciever interfaces being tested using PRBS data.
Intuitively, I think the motivation is to test the medium using a signal of somewhat even ...
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Problem in locating and stopping radiation from an ethernet phy and RMII signaling
An FCC unintentional radiators test is failing at 550MHz, after probing with a near field probe the source was located to these areas of the PCB (shown below in black circles). The RMII is running at ...
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PCIe x1 risers missing various signals - a hack or a legitimately allowed configuration?
Background
While debugging a system where one of the peripherals was only intermittently present on the bus, I turned my attention to PCIe risers as a culprit. After measuring a few of them I noticed ...
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How am I supposed to drive 50-Ohm terminated "CMOS inputs" (of AD9545 Evaluation Board)
The AD9545 Evaluation Board documentation states that the Reference Inputs (REF B/BB) are "configured for single-ended CMOS inputs" and drive the AD9545 via an "on board voltage divider&...
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Ethernet cable termination
I am using a D-coded M12 Ethernet connector in my device for a Fast Ethernet (100 Mbps) connection. Due to physical limitations, the connector can't be PCB-mounted, so I selected a panel-mount version ...
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Why don't PCB trace width calculation tools have an option for setting the currect capacity? Kicad tool as an example
I am using the Kicad trace width calculator tool for finding the width required for a 50 ohm trace.
The obtained value of trace width is 0.355mm. Assume this trace width is not enough for the ...
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What is the relation between pcb trace width and number of layers
I need to design a PCB for RF Application.
The board contains jsut 4 sma connectors .They are Connected as shown below.
The frequency of operation is 20Ghz. Trace impedance should be 50 Ohm.Current ...
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Which is a better routing with less crosstalk for diff pairs for Ethernet 100BaseT
I saw some routing the other day in a design, I'm wondering what would be better for less crosstalk. Version 1 has better matching but the diff pairs are closer to each other. Version 2 has better ...
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How can I add a small (~1 V) voltage from a fast, 50-ohm signal generator (AWG) onto a high DC voltage (~500 V) signal?
I need to add a small (~1 V) voltage with DC and AC (but not exclusively AC) components from a signal generator to a high DC voltage, up to approx. 500 V.
Conceptually, the answer could look like ...
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Soldering RG179 coaxial cable directly to PCB
I'm building a very low-cost bidirectional SDI-3G to fiber converter. I am in the process of selecting a connector for the SDI part. The issue is that I can't really find one that won't explode the ...
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Selecting a high-speed HDMI connector
I'm looking to build a mostly-passthrough HDMI device, but I'm finding it very confusing to understand the maximum speed that a connector can allow for.
I've noticed that DigiKey, for example, shows &...
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How important is a "no reflection" strategy for 1 Hz systems?
One of my colleagues claims that no matter what frequency the PCB board has, you cannot allow reflections inside the tracks. In this case, it's 1 Hz frequency that is going to turn a relay ON. The ...
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High frequency digital (2GHz+) and PCB manufacturability with FR4?
I have done many designs below 2GHz but am now needing to go beyond that to 3GHz. The PCB's need to be able to support MIPI CSI and LPDDR5 signaling. Can I use run of the mill FR4 or do I need to '...
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Why does a MOSFET fail on fast signals, even if they're much longer than the turn on + turn off times?
When running at a fast signal, why does the MOSFET below not turn off, even when gate voltage is well below threshold (even negative)? Although the signal is fast (7 MHz, 140 ns period) it is < 1/...
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How are pad impedance discontinuities precisely compensated for in high speed PCB layouts?
I stumbled across a recommendation in an 850MHz opamp datasheet that said the following:
All ground and power planes under the input and output pins must be cleared of copper to prevent the formation ...
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Display port eye diagram evaluation
I was testing my display port diagram, all 4 lines.
The first three look good, the 4th line looks like it has only one signal (not differential.)
My question:
Is the 4th line okey to be like this. (...
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Oscilloscope slow sampling with GPIB
I have a 12 GHz oscilloscope with a 40 GSa/s sampling rate from Keysight, and I have a National Instruments GPIB-USB-HS with it. Sampling for 30 seconds with no averaging of data, it only gives 20 ...
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Should reference plane change its potential value if a track goes to another layer?
Assume you have a four layer board.
Signal
GND
Dielectric
VDD
Signal
And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.
Question
The ...
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Noise Fluctuation with MAX40660
I am currently implementing MAX40660 as a high speed TIA amplifier. In the process of testing the basic functionality of the circuit, I have implemented a pcb design similar to the evaluation kit. ...
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Removing GND and Power planes under the feedback pins and traces in opamp layout
I want to use a reference design form Texas instrument as a reference for my layout for OPA838, I noticed this reference design is a 4-layer board (signal-GND-Power-signal):
Reference: the image is a ...
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How can I analyze HighSpeed traces what on Proteus project file?
I designed a few PCB on Proteus what includes High-Speed signal traces(USB, Displayport, GigaEthernet etc.). I want to analyze that High-Speed Traces. I expect see some values like eye diagrams, ...
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What happens if there is an impedance mismatch on differential pairs? [closed]
What do we encounter if the impedance changes along the way? For example, what kind of problem can we encounter when one of the two complementary PCB's is 90 ohm and the other is 100 ohm? For example, ...
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Which of these 2 phenomena occur first - AN or MDIX
Most of these days, the Ethernet PHY/switch devices support Auto-MDIX and Autonegotiation.
So, when a link partner is getting connected to a PHY or a Switch, which of these two phenomenons happens ...
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118
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How to achieve 50 Ohm Impedance with a SMB connector
I have a PCB design with a SMB connector but can't find any information about how I should treat the pad to ensure 50R impedance.
Should there be a keepout on the ground layer directly beneath this ...
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Why does this pulse generator have a voltage inverter?
I am designing a fast pulse generator, inspired by Leo Bodnar's pulse generator, using the ADCMP572 ultra fast comparator.
It looks like a pretty simple device, using a PIC microcontroller to drive ...
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Can I measure the internal termination resistance of a MIPI receiver?
This question is further to: How accurate are internal terminators on chips with high speed differential inputs?.
I would like to measure the actual termination resistance inside one of these chips (...
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Is a gap needed with LVDS with metal layer below it?
I have a 1.8 V, 350 MHz, 100 Ω LVDS signal on an FFC on the bottom plane. Below the FFC is an aluminum metal layer; the aluminum is pretty much unconnected from the FFC. The air gap/solder mask gap is ...
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FT2232H PCB routing (high speed)
This is the first time I am making a high speed PCB so I am a bit unconfident.
the ic I am talking about is this: FTDI232H
I have followed the schematic in the datasheet above and I have placed the ...
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How accurate are internal terminators on chips with high speed differential inputs?
I'm aware that due to process variation, some analog parameters of semiconductor devices can vary; sometimes quite a lot. (E.g. the SST3904 transistor specifies a DC current gain somewhere between 100 ...
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What on earth could be causing MIPI frame drops?
In a project I'm working on, we're seeing regular frame drops on a 1-lane, 900Mbps MIPI CSI-2 interface. After some investigating, I'm fairly sure that the problem is related to signal integrity. ...
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Is there some low power and fast circuit to move non-consecutive bit 1s to consecutive bit 1s (packing the bit 1s)? [closed]
Given n bits, for example, 00100110110001, there are six 1s in these bits.
I want to output 11111100000000, which moves the non-consecutive bit 1s to the left of the string.
I know some sequential ...
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PCB Build-Up and Stack-Up alternative for 8-layer PCB
I am looking at an open-source design for an NVIDIA Jetson Nano carrier board made by a company called AntMicro. See here
The design is an 8-layer design with the following Stack-Up and Build-Up ...
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DDR4 Routing Consideration on pcb (no DIMM)
I need to route DDR4x2(3200MHz) to my FPGA.
my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB.
my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
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Signal integrity with a gap in the ground plane
I see many people with some knowledge of PCB design, says it is bad practice to run high-speed signals of a "disconnected" ground place adjacent to the signal.
But no one shows practically ...
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How to know what length of via-stub is acceptable for a given signal?
This question is specifically about PCB layout for high speed memory interface: DDR3, DDR4, DDR5. I can see that often people would use microvias for high speed interfaces. The board I have seen was ...
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USB to FTDI connection
I try to connect USB 2.0 to a FTDI FT2232HL. This is my first high speed layout.
I am planning to use 2-layer board 1.6 mm. I know that I have to keep 50 Ω Z0 and 90 Ω Zdiff. However with the 2-layer ...
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Level shifting from 3.3 V to 1.8 V at 500 MHz
How can I translate a unidirectional signal from 3.3 V to 1.8 V with a bandwidth of 500 MHz?
The signal I am interested in is the output of a high speed comparator (TLV3601) and I have to measure the ...
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Z0 (resistive) high bandwidth, probe design
I plan to make a high-speed resistive probe according to the book "High-speed digital design: A Handbook of Black Magic". There is one thing I don't understand there:
Why this probe (unlike ...
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What is the copper frame around this high speed input signal called?
I was watching a teardown video for a scope and saw that the high speed input circuit has a copper frame around each input.
What is the purpose of this and what is it called?
It has a heatsink on top ...
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Issues with vias on ethernet differential signals in routing [duplicate]
I have ethernet differential signals and a discrete magnetics part.
I want to know what issues might arise if I place vias on the differential signals when connecting them between the magnetics and ...
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Is specific resistor and capacitor material type required for termination of high speed lines on PCB?
Most resistors will be metal film (aka thin film) and most capacitors will be ceramic (class II dielectric). Small components have less parasitive inductance than larger ones.
There are different type ...
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How to read a TDR report?
This is the report generated from Keysight ADS. I can see the reflections from the vias and layer change (impedance swing) but I couldn't figure out the impedance of the actual traces. Also, why are ...
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Trace Width, Length, and Clearance for SATA signals in KiCad PCB Design
I am looking to design a SATA adapter board which interfaces an FPGA LPC FMC connector with a SATA connector. This board will contain the 6 signals (RX+, RX-, TX+, TX-, and Clk+, Clk-) along with ...
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USB3.0 Differential Pair Eye Diagram - Transmitter Issues
Used the SI Power Aware analysis on the DP/DM signals for this simulation:
I'm having more issues on my Tx rather than the Rx. I do understand the Rx eye diagram but I'm struggling with the wild ...
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Predicting EMI/EMC Issues from Microcontroller AC Spec Rise time fall time
In one of his video Rick Hartley says signals with fast rise time can cause EMI/EMC issues.
I am using FS32K148UJT0VLQT in my design. In my board this controller is working at 5 V supply.
Below image ...
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PCB Ground Plane Cut-out
I saw these lines in a data sheet:
"To reduce unwanted capacitance, TI recommends cutting out the power and ground traces underneath the signal input and output pins. Otherwise, ground and power ...
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How power plane acts as a path for the return currents
In some pcb stackup's I can see that the power plane is given as reference to signal layers.
I have some questions regarding this.
May I know in that case how the return current flows.
Assume all my ...
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High-speed channel design
I am currently designing a host board for SFP+ modules. My premise is that I have never designed for high speed therefore I looked up online for application notes and sample boards.
I have mainly 3 ...
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Decoupling Capacitor voltage Selection
In my board there are many IC's present and for all these IC's it's manufacturers specified the decoupling capacitors.
When I generated my initial BOM what I observed is 99% of these capacitors are of ...
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