I did some comparing of properties of silicon mosfets to GaN (capacitances, package properties, thermal properties). I could find no real differences except one.
I also found that all 'regular' silicon mosfets have a similarly shaped SOA to each other, there are two methods to find SOA one is calculated and the other is measured (not all manufactures measure SOA some calculate it based off of other specs, TI has been measuring since 2014, but the measured SOAs for a regular mosfet look like the calculated values and all silicon mosfets have similar curves).
Another interesting fact the SOA for other GaNs look similar (this GaN part has almost all or very similar specs to the one in the OP) and also has that weird SOA curve:
https://www.transphormusa.com/wp-content/uploads/2020/02/tp65h035wsqa_v1-1.pdf
This means the problem is most likely related the properties of a GaN, but what?
The main difference I could find when comparing datasheets is the "Transient thermal impedance from junction to mounting base" as a function of pulse duration" This is an example from a/the GaN device:
Source: https://assets.nexperia.com/documents/data-sheet/GAN041-650WSB.pdf
Transient thermal impedance from junction to mounting base is the thermal resistance and mass that impedes heat from moving from the die to the case. We want heat to move to the case (and then to a heatsink, pcb or air) to keep the temperature down.
A device subjected to a power pulse of duration > ~1 second, i.e.
steady-state, has reached thermal equilibrium and the Zth plateaus
becomes the Rth. The Zth illustrates the fact that materials have
thermal inertia. Thermal inertia means that temperature does not
change instantaneously. As a result, the device can handle greater
power for shorter duration pulses
Source: https://assets.nexperia.com/documents/application-note/AN11261.pdf
This is an example from a regular silicon device.
Source: https://assets.nexperia.com/documents/data-sheet/PSMN057-200P.pdf
A normal Fet has better thermal conductivity (these graphs are hard to compare so I pulled out some 'rough' values)
A single pulse with a 1ms duration has 0.11K/W for silicon and 0.2K/W for GaN
A single pulse with a 10ms duration has 0.3 K/W for silicon and 0.6K/W for GaN
A duty cycle of \$\delta=0.1\$ with a 1ms duration has 0.15K/W for silicon and 0.2K/W for GaN
The GaN is about half as good as silicon at moving heat out from the die to the package with shorter pulses where \$\delta<0.5\$. This could be from many factors but I suspect it is from device construction.
GaN as a material has similar thermal conductivity to silicon (and has better properties than silicon in everything else except electron mobility, which probably has no bearing on how much heat a device can handle).
I don't think its the material properties in and of themselves that would drive the differences in thermal impedance so it is more likely that it is the construction of the device:
Source: https://spectrum.ieee.org/semiconductors/materials/gallium-oxide-power-electronics-cool-new-flavor
Another interesting thing to note is the GaN's seem to be worse in the thermal stability region, which means for longer pulses and higher Vds voltages they are more prone to get into a thermal runaway situation. I think this could correlate with the difference in thermal performance at short duration's and is probably the answer, but there probably won't be a infinitive answer without talking to a designer, or dencapsulating\reverse engineering devices.
Source: https://e2e.ti.com/blogs_/b/powerhouse/posts/understanding-mosfet-data-sheets-part-2-safe-operating-area-soa-graph
And another interesting graph is for an SiC device, I didn't delve into it but it has a similar SOA and junction to case thermal impedance as a silicon device.
Source: https://www.wolfspeed.com/media/downloads/1628/C3M0060065D.pdf
Edit (the internet continues to astound me):
I did find pics of a teardown for the part in the same family, the GAN063-650WSA! ( and same package which means the looks similar or maybe exactly the same)!
Source: https://www.systemplus.fr/reverse-costing-reports/nexperias-aec-q101-qualified-650-v-gan-based-power-device/
The GaN is cascoded, so it is actually two FETs
Source: https://assets.nexperia.com/documents/data-sheet/GAN041-650WSB.pdf
For a single FET
Both the cascode\silicon FET and the GAN FET generate heat with their bulk resistivity, and this heat has to move toward the gate.
The heat from the silicon FET has more material that it needs to pass through to reach the heatsink (the epoxy is not as good at conducting heat). This results in two slopes of the SOA graph. The silicon cascode FET will also likely be one of the hottest areas in the device. (which makes me wonder if cascoded GaN isn't really that competitive as a switching device as the SiC device listed in this question has no such limits. It also makes me wonder if there aren't ways to improve GaN.
However, I did find some SiC FETS that (are advertised as) are cascoded, but they have no weird SOA (That device is here: https://unitedsic.com/datasheets/DS_UJ3C120040K3S.pdf), I didn't find the construction of that device, but in the end I think it's construction more than anything that determines the SOA along with the thermal stackup.
Source: https://www.st.com/resource/en/application_note/dm00241971-thermal-effects-and-junction-temperature-evaluation-of-power-mosfets-stmicroelectronics.pdf
The link above is a really good read if you ever need to do modeling on FET thermal internals.
Above is a screenshot of the SOA graph from the GAN041-WSB350 datasheet.
